Wire planning for performance and yield enhancement

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 113-116

  Ouyang, Charles ^a   Ryu, Kyungsuk ^a   Heineken, Hans ^a   Khare, Jitu ^a   Shaikh, Saghir ^a   d'Abreu, Manuel ^a  

^a Level One Communications   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; INTEGRATED CIRCUIT MANUFACTURE; PLANNING; PRODUCTIVITY; WIRE;

DEEP SUBMICRON TECHNOLOGY; WIRE PLANNING STRATEGY; YIELD ENHANCEMENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033711824     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)