Low power CMOS design challenges

IEICE Transactions on Electronics

Volumn E84-C, Issue 8, 2001, Pages 1021-1028

  Kuroda, T ^a  

^a KEIO UNIVERSITY   (Japan)

Author keywords

Downsizing; Low power CMOS design; Low voltage; Subthreshold leakage current; Threshold voltage

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY EFFICIENCY; LEAKAGE CURRENTS; POWER CONTROL; POWER INTEGRATED CIRCUITS; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

LOW POWER DESIGN; POWER DISSIPATION; POWER REDUCTION; TECHNOLOGY SCALING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035421286     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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