Microprocessor reliability performance as a function of die location for a 0.25μ, five layer metal CMOS logic process

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 1999, Pages 1-11

  Riordan, Walter Carl ^a   Miller, Russell ^a   Sherman, John M ^a   Hicks, Jeffrey ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEFECTS; FAILURE ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; METALLIZING; MICROPROCESSOR CHIPS; TITANIUM COMPOUNDS;

CMOS LOGIC PROCESS; DEFECT DENSITY; DIE LEVELS ANALYSIS; FUSE TECHNOLOGY; INFANT MORTALITY; SHALLOW TRENCH ISOLATION; TRACEABILITY;

RELIABILITY THEORY;

EID: 0032639191     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (0)