Delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs

Proceedings of the International Symposium on Low Power Design

Volumn , Issue , 1998, Pages 48-53

  Miyazaki, Masayuki ^a   Mizuno, Hiroyuki ^a   Ishibashi, Koichiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DELAY LINES; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; LEAKAGE CURRENTS; LSI CIRCUITS; OSCILLATORS (ELECTRONIC); SUBSTRATES; THRESHOLD VOLTAGE;

DELAY FLUCTUATION DETECTOR; DIGITAL DELAY LOCKED LOOP; OPERATING FREQUENCY;

CMOS INTEGRATED CIRCUITS;

EID: 0031623211     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)