Logic synthesis of multilevel circuits with concurrent error detection

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 7, 1997, Pages 783-789

  Touba, Nur A ^a,b   McCluskey, Edward J ^a,b  

^a STANFORD UNIVERSITY   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR DETECTION; LOGIC DESIGN; OPTIMIZATION;

CONCURRENT ERROR DETECTION; MULTILEVEL CIRCUITS;

ELECTRIC NETWORK SYNTHESIS;

EID: 0031177081     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.644041     Document Type: Article

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