New methods for evaluating the impact of single event transients in VDSM ICs

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2002-January, Issue , 2002, Pages 99-107

  Alexandrescu, D ^a   Anghel, L ^b   Nicolaidis, M ^a  

^a iRoC Technologies   (France)

^b TIMA LABORATORY   (France)

Author keywords

Circuit faults; Circuit simulation; Combinational circuits; Discrete event simulation; Latches; Logic circuits; Noise reduction; Power supplies; Protection; Statistical analysis

Indexed keywords

CIRCUIT SIMULATION; COMBINATORIAL CIRCUITS; DEFECTS; DIGITAL STORAGE; DISCRETE EVENT SIMULATION; ELECTRIC NETWORK ANALYSIS; FAULT DETECTION; FAULT TOLERANCE; FLIP FLOP CIRCUITS; HIGH ELECTRON MOBILITY TRANSISTORS; LOGIC CIRCUITS; NOISE ABATEMENT; OPTIMIZATION; RADIATION HARDENING; STATISTICAL METHODS; VLSI CIRCUITS;

CIRCUIT FAULTS; COMBINATIONAL LOGIC; EVENT-DRIVEN SIMULATORS; FAULT SIMULATION; POWER SUPPLY; PROTECTION; SINGLE EVENT TRANSIENTS; TRANSIENT FAULTS;

TRANSIENTS;

EID: 84948970652     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2002.1173506     Document Type: Conference Paper

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