Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor

IEEE Transactions on Nuclear Science

Volumn 47, Issue 6 III, 2000, Pages 2609-2615

  Massengill, L W ^a,b   Baranski, A E ^a,b   Van Nort, D O ^a,b   Meng, J ^c   Bhuva, B L ^a,b  

^a IEEE   (United States)

^b VANDERBILT UNIVERSITY   (United States)

^c Silvaco Data Systems Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BITSLICE PROCESSOR; SINGLE EVENT UPSET EFFECTS;

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; SEQUENTIAL CIRCUITS;

COMPUTER SIMULATION;

EID: 0034452351     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.903816     Document Type: Conference Paper

References (7)

1. Attenuation of single event induced pulses in CMOS combinational logic
2. Comparison of error rates in combinational and sequential logic
3. Single-event upset cross-section modeling in combinational CMOS logic circuits
4. Simulation of design dependent failure exposure levels of CMOS ICs
5. Investigations of single-event upsets and charge collection in micro-electronics using variable-length laser-generated charge tracks
6. Techniques of microprocessor testing and SEU-rate prediction
7. Honeywell radiation hardened 32-bit processor single event effects test results