Approaches to using Al2O3 and HfO2 as gate dielectrics for CMOSFETs

Fujitsu Scientific and Technical Journal

Volumn 39, Issue 1, 2003, Pages 94-105

  Sugiyama, Yoshihiro ^a   Pidin, Sergey ^a   Morisaki, Yusuke ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; COBALT COMPOUNDS; DIELECTRIC MATERIALS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; HIGH TEMPERATURE OPERATIONS; NITROGEN COMPOUNDS; RELIABILITY; SEMICONDUCTING ALUMINUM COMPOUNDS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DOPING; THERMODYNAMIC STABILITY;

COBALT SILICIDE; DIMETHYLHYDRASIN; GATE DIELECTRICS; HIGH-TEMPERATURE ANNEALING;

MOSFET DEVICES;

EID: 0043202982     PISSN: 00162523     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (30)

1. D. K. Nayak, J. C. Woo, J. S. Park, K. L. Wang, and K. P. MacWilliams: High-Mobility p-Channel Metal-Oxide-Semiconductor Field-Effect Transistor on Strained Si. Appl. Phys. Lett., 62, 22, p. 2853-2855 (1993).
2. J. Welser, J. L. Hoyt, and J. F. Gibbons: Electron Mobility Enhancement in Strained-Si N-Type Metal-Oxide-Semiconductor Field-Effect Transistors. IEEE Electron Device Lett., EDL-15, 3, p.100-102 (1994).
3. M. Shima, T. Ueno, T. Kumise, H. Shido, Y. Sakuma, and S. Nakamura: <100> Channel Strained-SiGe p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance. Technical Digest of Symposium on VLSI Technology, p.94, 2002.
4. B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M.-R. Lin. 15nm Gate Length Planar CMOS Transistor. Technical Digest of IEDM, p.937, 2001.
5. M. Togo, K. Watanabe, T. Yamamoto, N. Ikarashi, K. Shiba, T. Tatsumi, H. One, and T. Mogami: Low-Leakage and Highly-Reliable 1.5 nm SiON Gate-Dielectric Using Radical Oxynitridation for Sub-0.1 μm CMOS. Technical Digest of Symposium on VLSI Technology, p. 116, 2000.
6. N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. T. Liu, R. C. Keller, and T. Horiuchi: NBTI Enhancement by Nitrogen Incorporation into Ultrathin Gate Oxide for 0.10-μm Gate CMOS Generation. Technical Digest of Symposium on VLSI Technology, p.92, 2000.
7. M. T. Takagi and Y. Toyoshima: Importance of Si-N Atomic Configuration at the Si/Oxynitride Interfaces on the Performance of Scaled MOSFETs. Technical Digest of IEDM, p.575. 1998.
8. 2 Gate Insulator with TiN Gate Technology for 0.1 μm MOSFETs. Technical Digest of Symposium on VLSI Technology, p. 135, 1997.
9. 2 Thickness. Technical Digest of IEDM, p.381, 1998.
10. K.J. Hubbard and D.G. Schlom: Thermodynamic Stability of Binary Oxides in Contact with Silicon. J. Mater. Res., 11, 11, p.2757-2775 (1996).
11. S. Miyazaki: Photoemission Study of Energy-Band Alignments and Gap-State Distributions for High-k Gate Dielectrics. J. Vac. Sci. Technol., B19, p.2212-2216 (2001).
12. 3 with Low Leakage and Low Interface States. Technical Digest of IEDM, p.605, 1998.
13. J. Robertson: Band Offsets of Wide-Band-Gap Oxides and Implications for Future Electronic Devices. J. Vac. Sci. Technol., B18, 3, p.1785-1791 (2000).
14. 2 Gate Dielectric. International Symposium on VLSI-TSA, p.204, 2001.
15. B. H. Lee, L. Kang, W.-J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J. C. Lee: Ultrathin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate Dielectric Application. Technical Digest of IEDM, p.133, 1999.
16. P. Alluri, S. Zafar, J. Conner, L. Prabhu, D. Roan, D. Gentile, B. Hradsky, J. Finder, R. Hedge, C. Hobbs, J. Schaeffer, D. Gilmer, H. Tseng, V. Kaushik, B. Y. Nguyen, P. Chu, and P. Tobin: Chemical Vapor Phase Grown High-k Gate Dielectrics. MRS High-k Gate Dielectric Workshop, p.27, 2000.
17. 2 Films. Appl. Phys. Lett., 81, 8, p.1441-1443 (2002).
18. E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn-Schmidt, C. D'Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L.-Å. Ragnarsson, P. Ronsheim, K. Rim, R. J. Fleming, A. Mocuta, and A. Ajmera: Ultrathin High-K Gate Stacks for Advanced CMOS Devices. Technical Digest of IEDM, p.451, 2001.
19. 2 Equivalent Thickness. Technical Digest of IEDM, p. 137, 2001.
20. 3 to Improve Electrical Characteristics of MOSF'ETs with Polysilicon Gate. Technical Digest of Symposium on VLSI Technology, p.190, 2002.
21. 2/Si MOSFET Performance. Technical Digest of IEDM, p. 655, 2001.
22. y). Technical Digest of Symposium on VLSI Technology, p.146, 2002.
23. inv = 1.7 nm) Poly-Si-gated SiN/HfO2/SiON High-k Stack Dielectrics with High Thermal Stability (1050°C). Technical Digest of IEDM, p.861, 2002.
24. 2 Gate Oxide for 100-nm Generation. Technical Digest of Symposium on VLSI Technology, p.28, 2002.
25. 2 Interface-Electrical Properties as Determined by the Metal-Insulator-Silicon Conductance Technique. Bell Syst. Tech. J., 46, 6, p.1055-1133 (1967).
26. E. M. Vogel, W. K. Hensen, C. A. Richter, and S. Suehle: Limitations of Conductance to the Measurement of the Interface State Density of MOS Capacitors with Tunneling Gate Dielectrics. IEEE Trans. Electron Devices, ED-47, 3, p.601-608 (2000).
27. S.-I. Saito, K. Torii, M. Hiratani, and T. Onai: Analytical Quantum Mechanical Model for Accumulation Capacitance of MOS Structures. IEEE Electron Device Lett., EDL-23, 6, p.348-350 (2002).
28. 2 Gate Stack. Proc. of Int. Reliability Phys. Symp., p.409, 2002.
29. 2 Gate Dielectric MOSFETs with TaN Electrode and Nitridation Surface Preparation. Technical Digest of Symposium on VLSI Technology, p. 31, 2001.
30. 2 Gate Dielectric. Technical Digest of IEDM, p.651, 2001.