Analytical quantum mechanical model for accumulation capacitance of MOS structures

IEEE Electron Device Letters

Volumn 23, Issue 6, 2002, Pages 348-350

  Saito, Shin Ichi ^b   Torii, Kazuyoshi ^b   Hiratani, Masahiko ^b   Onai, Takahiro ^a,b  

^a IEEE

^b HITACHI LTD   (Japan)

Author keywords

Accumulation; Capacitance; Equivalent oxide thickness; High gate dielectrics; MOS devices; Quantization

Indexed keywords

BOUNDARY CONDITIONS; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC POTENTIAL; GATES (TRANSISTOR); MATHEMATICAL MODELS; PERMITTIVITY; POISSON EQUATION; POLYSILICON; QUANTUM THEORY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES;

CAPACITANCE VOLTAGE CHARACTERISTICS; CHARGE DENSITY; CHARGE DISTRIBUTION; CHEMICAL POTENTIAL; EQUIVALENT OXIDE THICKNESS; GATE DIELECTRICS; GAUSS LAW; QUANTUM STATISTICS; SCHRODINGER EQUATION; SURFACE POTENTIAL;

MOSFET DEVICES;

EID: 0036611166     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2002.1004231     Document Type: Letter

References (7)

1. High-κ gate dielectrics: Current status and materials properties considerations
2. A comparison of quantum-mechanical capacitance-voltage simulators
3. Electronic properties of two-dimensional systems
4. Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFETs
5. Polysilicon quantization effects on the electrical properties of MOS transistors
6. Understanding the effects of wave function penetration on the inversion layer capacitance of NMOSFETs