On-the-fly reseeding: A new reseeding technique for test-per-clock BIST

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 3, 2002, Pages 315-332

  Kalligeros, Emmanouil ^a,b   Kavousianos, Xrysovalantis ^a,b   Bakalis, Dimitris ^a,b   Nikolos, Dimitris ^a,b  

^a UNIVERSITY OF PATRAS   (Greece)

^b University of Patras and Computer Technology Institute   (Greece)

Author keywords

Accumulator based test pattern generators; Built in self test; Linear feedback shift registers; Reseeding; Test per clock schemes

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); CALCULATIONS; COMPUTER SIMULATION; FAILURE ANALYSIS; FLOWCHARTING; LOGIC DESIGN; LOGIC GATES; POLYNOMIALS; SHIFT REGISTERS;

LINEAR FEEDBACK SHIFT REGISTER; RESEEDING TECHNIQUE; TEST PATTERN GENERATOR; TEST-PER-CLOCK TEST PATTERN GENERATION;

BUILT-IN SELF TEST;

EID: 0036605298     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1015039323168     Document Type: Conference Paper

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