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Volumn , Issue , 2001, Pages 156-160

On applying the set covering model to reseeding

Author keywords

[No Author keywords available]

Indexed keywords

DETERMINISTIC TEST PATTERN; FUNCTIONAL MODULES; OPTIMAL RESEEDING; SET COVERING PROBLEM; SET-COVERING MODEL; SYSTEM FUNCTIONALITY; TEST SET ENCODING; TESTING TECHNIQUE;

EID: 0009022223     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915017     Document Type: Conference Paper
Times cited : (15)

References (18)
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    • Gupta, S.1    Rajski, J.2    Tyszer, J.3
  • 3
    • 84961240995 scopus 로고
    • Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers
    • S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers, IEEE ITC, 1992, pp. 120-129
    • (1992) IEEE ITC , pp. 120-129
    • Hellebrand, S.1    Tarnick, S.2    Rajski, J.3    Courtois, B.4
  • 5
    • 0030651782 scopus 로고    scopus 로고
    • Methods to reduce test application time for accumulator-based self-test
    • A. P. Stroele, F. Mayer, Methods to reduce Test Application Time for Accumulator-Based Self-Test, IEEE VTS, 1997, pp. 48-53
    • (1997) IEEE VTS , pp. 48-53
    • Stroele, A.P.1    Mayer, F.2
  • 11
    • 0000718899 scopus 로고
    • The map method for synthesis of combinational logic circuits
    • M. Karnaugh, The Map Method for Synthesis of Combinational Logic Circuits, Transaction IEEE, vol. 72, pp 593-599, 1953
    • (1953) Transaction IEEE , vol.72 , pp. 593-599
    • Karnaugh, M.1
  • 14
    • 0017005672 scopus 로고
    • Microprogram Optimization: A Survey
    • October
    • T. Agrawala, Microprogram Optimization: A Survey, IEEE Trans. Comp., pp. 962-973, October 1976
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    • Agrawala, T.1
  • 15
    • 0027629018 scopus 로고
    • COMPACTEST: A method to generate compact test sets for combinational circuits
    • July
    • I. Pomeranz, L. N. Reddy, S. M. Reddy, COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits, IEEE Trans, on CAD, pp. 1040-1049, July 1993
    • (1993) IEEE Trans, on CAD , pp. 1040-1049
    • Pomeranz, I.1    Reddy, L.N.2    Reddy, S.M.3
  • 17
    • 33845331515 scopus 로고
    • Minimization of boolean functions
    • April
    • E. L. Jr. McCluskey, Minimization of Boolean Functions, Bell. Sys. Tech. Jour., vol. 35, pp. 1417-1444, April 1959
    • (1959) Bell. Sys. Tech. Jour. , vol.35 , pp. 1417-1444
    • McCluskey Jr., E.L.1
  • 18
    • 84893670726 scopus 로고    scopus 로고
    • http://www.synopsys.com


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.