메뉴 건너뛰기




Volumn 1, Issue , 2000, Pages I-72-I-75

Built-in self testing of high-performance circuits using twisted-ring counters

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT TESTING;

EID: 0033685326     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2000.857029     Document Type: Article
Times cited : (20)

References (10)
  • 1
    • 0003972145 scopus 로고
    • Built-in Test for VLSI. Pseudorandom Techniques
    • John Wiley and Sons NY, New York
    • P. Bardell W. McAnney J. Savir Built-in Test for VLSI. Pseudorandom Techniques 1987 John Wiley and Sons NY, New York
    • (1987)
    • Bardell, P.1    McAnney, W.2    Savir, J.3
  • 2
    • 0032661192 scopus 로고    scopus 로고
    • Built-in pattern generation for high-performance circuits using twisted-ring counters
    • K. Chakrabarty B. T. Murray V. Iyengar Built-in pattern generation for high-performance circuits using twisted-ring counters Proc. 1999 IEEE VLSI Test Symposium 22 27 Proc. 1999 IEEE VLSI Test Symposium 1999
    • (1999) , pp. 22-27
    • Chakrabarty, K.1    Murray, B.T.2    Iyengar, V.3
  • 4
    • 0031361729 scopus 로고    scopus 로고
    • On using machine learning for logic BIST
    • C. Fagot P. Girard C. Landrault On using machine learning for logic BIST Proc. Int. Test Conf. 338 346 Proc. Int. Test Conf. 1997
    • (1997) , pp. 338-346
    • Fagot, C.1    Girard, P.2    Landrault, C.3
  • 5
    • 0032320384 scopus 로고    scopus 로고
    • Test set compaction algorithms for combinational circuits
    • I. Hamzaoglu J. H. Patel Test set compaction algorithms for combinational circuits Proc. Int. Conf. CAD 283 289 Proc. Int. Conf. CAD 1998
    • (1998) , pp. 283-289
    • Hamzaoglu, I.1    Patel, J.H.2
  • 6
    • 0029534112 scopus 로고
    • Pattern generation for a deterministic scheme
    • S. Hellebrand B. Reeb S. Tarnick H. Wunderlich Pattern generation for a deterministic scheme Proc. Int. Conf. CAD 88 94 Proc. Int. Conf. CAD 1995
    • (1995) , pp. 88-94
    • Hellebrand, S.1    Reeb, B.2    Tarnick, S.3    Wunderlich, H.4
  • 7
    • 0031340064 scopus 로고    scopus 로고
    • Using BIST control for pattern generation
    • G. Kiefer H. Wunderlich Using BIST control for pattern generation Proc. Int. Test Conf. 347 355 Proc. Int. Test Conf. 1997
    • (1997) , pp. 347-355
    • Kiefer, G.1    Wunderlich, H.2
  • 8
    • 0003581572 scopus 로고    scopus 로고
    • On the Generation of Test Patterns for Combinational Circuits
    • H. K. Lee D. S. Ha On the Generation of Test Patterns for Combinational Circuits 12.93 Dept. of Electrical Eng., Virginia Tech.
    • Lee, H.K.1    Ha, D.S.2
  • 9
    • 85177139201 scopus 로고    scopus 로고
    • Silicon Industry Association (SIA) 1997 The National Technology Roadmap for Semiconductors (NTRS) http://notes.sematech.org/97pelec.htm
    • (1997)
  • 10
    • 0027842914 scopus 로고
    • On-chip test generation for combinational circuits by LFSR modification
    • S. J. Upadhayaya L.-C. Chen On-chip test generation for combinational circuits by LFSR modification Proc. 1993 International Conference on CAD 84 87 Proc. 1993 International Conference on CAD 1993
    • (1993) , pp. 84-87
    • Upadhayaya, S.J.1    Chen, L.-C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.