Crosstalk effects in mixed-signal ICs in deep submicron digital CMOS technology

Microelectronics Journal

Volumn 31, Issue 11-12, 2000, Pages 893-904

  Liberali, V ^a   Rossi, R ^a   Torelli, G ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; CROSSTALK; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT;

MIXED-SIGNAL INTEGRATED CIRCUITS; SOFTWARE PACKAGE SPICE;

CMOS INTEGRATED CIRCUITS;

EID: 0034501640     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2692(00)00081-1     Document Type: Article

References (47)

1. Intel Corp., What is Moore's Law? Available at URL http://www.intel.com/intel/museum/25anniv/hof/moore.htm.
2. J. Borel, LP/LV circuits in the deep submicron area, Proceedings of the 1997 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Baveno, Italy, September 1997, pp. 8-13.
3. Semiconductor Industry Association (SIA), The International Technology Roadmap for Semiconductors, 1999. Available at URL http://public.itrs.net/1999_SIA_Roadmap/Home.htm.
4. H. Iwai, Silicon MOSFET scaling beyond 0.1 micron, Proceedings of the 21st International Conference on Microelectronics (MIEL '97), Niš, Yugoslavia, September 1997, pp. 11-18.
5. H. Samueli, Broadband communication ICs: enabling high-bandwidth connectivity in home and at office, IEEE International Solid-State Circuit Conference Digest of Technical Papers, San Francisco, CA, USA, February 1999, pp. 26-30.
6. Johns D.A., Essig D. Integrated circuits for data transmission over twisted-pair channels. IEEE J. Solid-State Circ. 32:1997;398-406.
7. J.P. Cornil, J. Sevenhans, P. Spruyt, M. Mielants, S. Braet, DMT ADSL and VDSL circuits and systems, Proceedings of the Workshop on Advances in Analog Circuit Design (AACD '99), Opio, France, March 1999.
8. Rauschmayer D.J. ADSL/VDSL Principles. 1999;Macmillan, Indianapolis, IN.
9. Y. Neuvo, Future directions in mobile communicators, Proceedings of the European Solid-State Circuit Conference, Neuchâtel, Switzerland, September 1996, pp. 35-39.
10. H. Nakatsuka, The new frontier created by high-bandwidth digital video systems and services in IEEE International Solid-State Circuit Conference Digest of Technical Papers, San Francisco, CA, USA, February 1999, pp. 16-19.
11. R.B. Joshi, et al., A 52 Mb/s universal DSL transceiver IC, IEEE International Solid-State Circuit Conference Digest of Technical Papers, San Francisco, CA, USA, February 1999, pp. 250-251.
12. Azadet K., Nicole C.J. Low-power equalizer architectures for high-speed modems. IEEE Commun. Mag. 36:1998;118-126.
13. L. Deferm, G. Badenes, Integration difficulties and limitations in sub-0.25 μm CMOS and CMOS-based technologies, Proceedings of the 22nd International Conference on Microelectronics (MIEL 2000); Niš, Yugoslavia, May 2000, pp. 399-406.
14. Verghese N.K., Allstot D.J., Wolfe M.A. Verification techniques for substrate coupling and their application to mixed-signal IC design. IEEE J. Solid-State Circ. 31:1996;354-365.
15. Felder M., Ganger J. Analysis of ground-bounce induced substrate noise coupling in a low resistive bulk epitaxial process: design strategies to minimize noise effects on a mixed-signal chip. IEEE Trans. Circ. Syst.-II. 46:1999;1427-1436.
16. Casalta J.M., Aragonès X., Rubio A. Substrate coupling evaluation in BiCMOS technology. IEEE J. Solid-State Circ. 32:1997;598-603.
17. Johnson T.A., Knepper R.W., Marcello V., Wang W. Chip substrate resistance modeling technique for integrated circuit design. IEEE Trans. Computer-Aided Design Integr. Circ. Syst. 3:1984;126-134.
18. B. Li, L.-R. Zheng, H. Tenhunen, Hierarchical modelling of sigma delta modulators for noise coupling analysis, Proceedings of the 1999 Southwest Symposium on Mixed-Signal Design (SSMSD '99), Tucson, AZ, USA, April 1999, pp. 58-62.
19. Chiprout E. Interconnect and substrate modeling and analysis: an overview. IEEE J. Solid-State Circ. 33:1998;1445-1452.
20. Gharpurey R., Meyer R.G. Modeling and analysis of substrate coupling in integrated circuits. IEEE J. Solid-State Circ. 31:1996;344-353.
21. Charbon E., Miliozzi P., Carloni L.P., Ferrari A., Sangiovanni-Vincentelli A. Modeling digital substrate noise injection in mixed-signal IC's. IEEE Trans. Computer-Aided Design Integr. Circ. Syst. 18:1999;301-310.
22. Stanisic B.R., Verghese N.K., Rutenbar R.A., Carley L.R., Allstot D.J. Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis. IEEE J. Solid-State Circ. 29:1994;226-238.
23. J.P. Costa, M. Chou, L.M. Silveira, Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's, Proceedings of the Design, Automation and Test in Europe, Paris, France, February 1998, pp. 892-898.
24. J.P. Costa, M. Chou, L.M. Silveira, Efficient techniques for accurate extraction and modeling of substrate coupling in mixed-signal IC's, Proceedings of the Design, Automation and Test in Europe, Munich, Germany, March 1999, pp. 396-400.
25. T. Liu, J.D. Carothers, W.T. Holman, A concurrent substrate coupling noise modelling technique for mixed-signal physical design, Proceedings of the 1999 Southwest Symposium on Mixed-Signal Design (SSMSD '99), Tucson, AZ, USA, April 1999, pp. 21-26.
26. H. Nakata and A. Iwata, A microscopic substrate noise model for full chip mixed-signal design verification, 1997 Symposium on VLSI Circuits Digest of Technical Papers, Kyoto, Japan, June 1997, pp. 37-38.
27. Samavedam A., Sadate A., Mayaram K., Fiez T.S. A scalable substrate noise coupling model for design of mixed-signal IC's. IEEE J. Solid-State Circ. 35:2000;895-904.
28. Su D.K., Loinaz M.J., Masui S., Wooley B.A. Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits. IEEE J. Solid-State Circ. 28:1993;420-430.
29. M. van Heiningen, J. Compiet, P. Wambacq, S. Donnay, I. Bolsens, A design experiment for measurement of the spectral content of substrate noise modelling in mixed-signal integrated circuits, Proceedings of the 1999 South-west Symposium on Mixed-Signal Design (SSMSD'99), Tucson, AZ, USA, April 1999, pp. 27-32.
30. Joardar K. A simple approach to model crosstalk in integrated circuits. IEEE J. Solid-State Circ. 29:1994;1212-1219.
31. Verghese N.K., Allstot D.J. Computer-aided design considerations for mixed-signal in RF integrated circuits. IEEE J. Solid-State Circ. 33:1998;314-323.
32. Weste N.H.E., Eshraghian K. Principles of CMOS VLSI Design: a System Perspective. 2nd ed. 1993;Addison-Wesley, Reading, MA.
33. K. Bult, Analog broadband communication circuits in pure digital deep sub-micron CMOS, IEEE International Solid-State Circuit Conference Digest of Technical Papers, San Francisco, CA, USA, February 1999, pp. 76-77.
34. Gonzales R., Gordon B.J., Horowitz M.A. Supply and threshold voltage scaling for low power CMOS. IEEE J. Solid-State Circ. 32:1997;1210-1216.
35. Chandrakasan A.P., Brodersen R.W. Low Power Digital CMOS Design. 1995;Kluwer Academic, Norwell, MA.
36. Hawley R.A., Wong B.C., Lin T., Laskowski J., Samueli H. Design techniques for silicon compiler implementation of high-speed FIR digital filters. IEEE J. Solid-State Circ. 31:1996;656-667.
37. Khoo K.-Y., Kwentus A., Wilson A.N. Jr. A programmable FIR digital filter using CSD coefficients. IEEE J. Solid-State Circ. 31:1996;869-874.
38. Senthilnathan R., Prince J.L. Simultaneous Switching Noise of CMOS Devices and Systems. 1994;Kluwer Academic, Norwell, MA.
39. Gabara T., Fischer W.C., Harrington J., Troutman W.W. Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers. IEEE J. Solid-State Circ. 32:1997;407-418.
40. S. Bobba, I.N. Hajj, Simultaneous switching noise in CMOS VLSI circuits, Proceedings of the 1999 Southwest Symposium on Mixed-Signal Design (SSMSD '99), Tucson, AZ, USA, April 1999, pp. 15-20.
41. Choi C.S., Ku M.H., Chan C.F. A low power-noise output driver with an adaptive characteristic applicable to a wide range of loading conditions. IEEE J. Solid-State Circ. 32:1997;913-917.
42. P. Erratico, The evolution of analog/digital interface in submicron IC's, Proceedings of the 1997 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Baveno, Italy, September 1997, pp. 1-7.
43. Redman-White W., et al. A robust analog interface system for submicron CMOS video DSP. IEEE J. Solid-State Circ. 33:1998;1076-1081.
44. Ingels M., Steyaert M.S.J. Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's. IEEE J. Solid-State Circ. 32:1997;1136-1141.
45. Lau J.H. Flip Chip Technologies. 1996;McGraw-Hill, New York.
46. H. Nagata, Y. Kashima, D. Tamura, T. Morie, A. Iwata, Measurements and analyses of substrate noise waveform in mixed signal IC environment, Proceedings of the 1999 Custom Integrated Circuit Conference, San Diego, CA, USA, May 1999, pp. 575-578.
47. Muller R.S., Kamins T.I. Device Electronics for Integrated Circuits. 1977;Wiley, New York.