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Volumn , Issue , 1997, Pages 8-13
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LP/LV circuits in the deep submicron area
a
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER AIDED DESIGN;
COST EFFECTIVENESS;
INTEGRATED CIRCUIT LAYOUT;
OPTIMIZATION;
POWER ELECTRONICS;
RESOURCE ALLOCATION;
SEMICONDUCTING SILICON;
SEMICONDUCTOR DEVICES;
TIMING CIRCUITS;
DEEP SUBMICRON TECHNOLOGY;
LOW POWER/LOW VOLTAGE CIRCUITS;
MICROELECTRONICS;
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EID: 0031359317
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (1)
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References (0)
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