A concurrent substrate coupling noise modeling technique for mixed-signal physical design

1999 Southwest Symposium on Mixed-Signal Design, SSMSD 1999

Volumn , Issue , 1999, Pages 21-26

  Liu, Tingyang ^a   Carothers, Jo Dale ^a   Holman, W Timothy ^a  

^a University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; COMPUTATION THEORY;

ANALYSIS TECHNIQUES; COMPUTATIONAL FEASIBILITY; CONCURRENT SIMULATION; HIERARCHICAL APPROACH; LOGIC SIMULATIONS; MODEL SUBSTRATES; MODELING TECHNIQUE; SUBSTRATE COUPLING NOISE;

SPICE;

EID: 39849096963     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSMSD.1999.768584     Document Type: Conference Paper

References (14)

1. David K. Su, Marc J. Loinaz, Shoichi Masui and Bruce A. Wooley, "Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits," IEEE Journal of Solid-state Circuits, Vol 28, No. 4, April 1993, pp.420-430.
2. Tallis Blalack, jack Lau, Francois J.R. Clement and Bruce A. Wooley, "Experimental Results and Modeling of Noise Coupling in a Lightly Doped Substrate," IEEE 1996 International Electron Devices Meeting, 1996, pp.23.3.1-23.3.4.
3. T. Blalack and B. Wooley, "The effects of Switching Noise on an Oversampling AID Converter," IEEE International Solid State Circuits Conference, 1995, pp.200-202.
4. Francois J.R. Clement, Eytan Zysman, Maher Kayal and Prof. Michal Declercq, "LAYIN: Toward a Global solution for Parasitic Coupling Modeling and Visualization," IEEE 1994 Custom Integrated Circuits Conference, 1994, pp.537-540.
5. Sujoy Mitra, Rob A. Rutenbar, L. Richard Carley and David J. Allstot, "Substrate-Aware Mixed-Signal Macrocell Placement in WRIGHT," IEEE Journal of Solid-State Circuits, Vol. 30, No. 3, March 1995, pp.269-278.
6. Ivan L. Wemple and Andrew T. Yang, "Integrated Circuit Substrate Coupling Models Based on Voronoi Tessellation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vo1.14, No.12, December 1995, pp.1459-1468.
7. T. Smedes, N.P. van der Meijs and A.J. van Genderen, "Extraction of Circuit Models for Substrate Cross-talk," IEEE/ACM International Conference on Computer-Aided Design, 1995, pp. 199-206.
8. Thomas A. Johnson, Ronald W. Knepper, Cictor marcello and Wen Wang, "Chip Substrate Resistance Modeling Technique for Integrated Circuit Design," IEEE Transactions on Computer-Aided Design, Vol. CAD-3, No.2, April 1984, pp. 126-134.
9. Kuntal Joardar, "A Simple Approach to Modeling Cross-Talk in Integrated Circuits," IEEE Journal of Solid-State Circuits, Vol. 29, No.10, October 1994, pp.1212-1219.
10. [lo] Balsha R. Stanisic, Rob A. Rutenbar, and L.Richard Carley, Addressing Noise Decoupling in Mixed-Signal IC's: Power Distribution Design and Cell Customization," IEEE Journal of Solid-State Circuits, Vol. 30, No. 3, March 1995, pp.321-326.
11. [ll] X. Aragones, F. Moll, M. Roca and A. Rubio, "Analysis and Modelling of Parasitic Substrate Coupling in CMOS Circuits," IEE Proc. Circuits Devices System, Vol. 142, No. 5, October 1995, pp. 307-312.
12. Juan M. Casalta, Xavier Aragones and Antonnio Rubio, "Substrate Coupling Evaluation in BiCMOS Technology," IEEE Journal of Solid-state Circuits, Vol. 32, No. 4, April 1997, pp.598-603.
13. R. Singh and S . Sali, "Efficient real-time modelling of substrate coupling in large mixed-signal Spice designs, using analogue HDL," IEE Proceedings-Circuits, Devices and Systems, Vol. 145, No. 3, June 1998, pp.180-184.
14. A.L.L. Pun, T. Yeung, J. Lau, J.R. Clement, D.K. Su, "Substrate noise coupling through planar spiral inductor," IEEE Journal of Solid-state Circuits, Vol. 33, No. 6, June 1998, pp.877-884.