Analysis of ground-bounce induced substrate noise coupling in a low resistive bulk epitaxial process: Design strategies to minimize noise effects on a mixed-signal chip

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 46, Issue 11, 1999, Pages 1427-1436

  Felder, Matt ^a   Ganger, Jeff ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE;

GROUND-BOUNCE INDUCED SUBSTRATE NOISE COUPLING; MIXED-SIGNAL CHIPS;

MICROPROCESSOR CHIPS;

EID: 0033343660     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.803483     Document Type: Article

References (7)

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