Injection efficiency of CHISEL gate currents in short MOS devices: physical mechanisms, device implications, and sensitivity to technological parameters

IEEE Transactions on Electron Devices

Volumn 47, Issue 11, 2000, Pages 2194-2200

  Esseni, David ^a   Selmi, Luca ^a   Ghetti, Andrea ^a  

^a UNIVERSITY OF UDINE   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENT DISTRIBUTION MEASUREMENT; ELECTRON DEVICE TESTING; GATES (TRANSISTOR); MATHEMATICAL MODELS; MONTE CARLO METHODS; MOSFET DEVICES; PARAMETER ESTIMATION; SEMICONDUCTOR DOPING; SENSITIVITY ANALYSIS;

CHANNEL DOPING; CHANNEL INITIATED SECONDARY ELECTRON INJECTION; CHARGE INJECTION; GATE CURRENTS;

MOS DEVICES;

EID: 0034315571     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.877183     Document Type: Article

References (28)

1. Y. Nakagome, E. Takeda, H. Kume.andS. Asai, "New observation of hot carrier injection phenomena," Jpn. J. Appl. Phys., vol. 22, p. 99, 1982.
2. J. D. Bude, "Gate current by impact ionization feedback in sub-micron MOSFET technologies," in Proc. Symp. VLSI Technology, 1995, p. 101.
3. J. D. Bude et al, "Secondary electron flash-A high performance, low power flash technology for 0.35 ftm and below," in IEDM Tech. Dig., 1997, p. 279.
4. M. Mastrapasqua, "Low voltage flash memory by use of a substrate bias," Microelectron. Eng., vol. 48, p. 389, 1999.
5. D. Esseni, A. Delia Strada, P. Cappelletti, and B. Riccö, "A new and flexible scheme for hot-electron programming of nonvolatile memory cells," IEEE Trans. Electron Devices, vol. 46, pp. 125-133, Jan. 1999.
6. C.-Y. Hu et al., "A convergence scheme for over-erased flash EEPROM's using substrate-enhanced hot electron injection," IEEE Electron Device Lett., vol. 11, p. 500, 1995.
7. C.-Y. Hu et al, "Substrate-current-induced hot electron (SCIHE) injection: A new convergence scheme for flash memory," in IEDM Tech. Dig., 1995, p. 283.
8. E. Takeda, "Hot carrier effects in submicrometer MOS VLSI's," Proc. Inst. Elec. Eng., vol. 131, p. 153, 1984.
9. L. Selmi and D. Esseni, "A better understanding of substrate enhanced gate current in MOSFET's and flash cells-Part II: Physical analysis," IEEE Trans. Electron Devices, vol. 46, p. 376, Feb. 1999.
10. D. Esseni and L. Selmi, "A better understanding of substrate enhanced gate current in MOSFET's and flash cells-Part I: Phenomenological aspects," IEEE Trans. Electron Devices, vol. 46, p. 369, Feb. 1999.
11. B. Eitan and D. Frohman-Bentchkowsky, "Hot-electron injection into the Oxide in n-channel MOS devices," IEEE Trans. Electron Devices, vol. ED-28, p. 328, 1981.
12. S. Tarn, P. K. Ko, and C. Hu, "Lucky-electron model of channel hotelectron injection in MOSFETs," IEEE Trans. Electron Devices, vol. ED-31, p. 1116, Sept. 1984.
13. C. Huetat., "Hot-electron-induced MOSFETdegradation: Model, monitor, and improvement," IEEE Trans. Electron Devices, vol. ED-32, p. 375, 1985.
14. D. Esseni and L. Selmi, "Experimental signature and physical mechanisms of substrate enhanced gate current in MOS devices," in IEDM Tech. Dig., 1998, p. 579.
15. D. Esseni, L. Selmi, A. Ghetti, and E. Sangiorgi, "The scaling properties of CHISEL and CHE injection efficiency in MOSFET's and flash memory cells," in IEDM Tech. Dig., 1999, p. 275.
16. F. Venturi and A. Ghetti, "Assessment of accuracy limitations of full band Monte Carlo device simulation," in Proc. SISPAD, 1997, p. 343.
17. M. V. Fischetti and S. Laux, "Monte Carlo study of sub-bandgap impact ionization in small Silicon field effect transistors," in IEDM Tech. Dig., 1995, p. 305.
18. "Monte Carlo simulation of electron transport in Si: The first 20 years," in Proc. Eur. Solid State Device Research Conf., 1996, p. 813.
19. D. L. Kencke et al., "The origin of secondary electron gate current: A multiple stage Monte Carlo study for scaled, low power flash memory," in IEDM Tech. Dig., 1998, p. 889.
20. F. A. Abramo and C. Fiegna, "Hot carrier effects in short MOSFET's at low applied voltages," in IEDM Tech. Dig., 1995, p. 301.
21. A. Ghetti, L. Selmi, and R. Bez, "Low voltage hot electrons and softprogramming lifetime prediction in nonvolatile memory cells," IEEE Trans. Electron Devices, vol. 46, p. 696, Apr. 1999.
22. B. Fischer et al., "Bias and temperature dependence of homogeneous hot-electron injection from Silicon into Silicon Dioxide at low voltages," IEEE Trans. Electron Devices, vol. 44, p. 288, Feb. 1997.
23. M. V. Fischetti, S. Laux, and E. Crabbè, "Understanding hot electron transport in Silicon Devices: Is there a shortcut?," J. Appl. Phys., vol. 78, p. 1058, 1995.
24. T. H. Ning, C. M. Osburn, and H. N. Yu, "Emission probability of hot electrons from silicon into silicon dioxide," J. Appl. Phys., vol. 48, p. 286, 1977.
25. J. Dickson, "On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique," IEEE J. SolidState Circuits, vol. SC-11, pp. 374-378, June 1976.
26. T. Tanzawa and T. Tanaka, "A dynamic analysis of the Dickson charge pump circuit,"IEEEJ. Solid State Circuits, vol. 33, pp. 1231-1240, Aug. 1997.
27. K. Yoshikawa et al, "A flash EEPROM cell scaling including tunnel Oxide limitations," in Proc. Eur. Solid-State Device Research Conf., 1990, p. P/2.
28. P. Pavan and R. Bez, "The industry standard flash memory cell," in Flash Memories, P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Eds. Boston, MA: Kluwer, 1999.