Possibilities and limitations of IDDQ testing in submicron CMOS

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 21, Issue 4, 1998, Pages 352-359

  Figueras, Joan ^a,b   Ferré, Antoni ^b  

^a IEEE   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

CMOS scaling trends; Current testing; Leakage power consumption; Quiescent currents

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT TESTING; LEAKAGE CURRENTS;

QUIESCENT CURRENT CONSUMPTION;

ELECTRONICS PACKAGING;

EID: 0032206006     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.730419     Document Type: Article

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