IDDQ testing: Issues present and future

IEEE Design and Test of Computers

Volumn 13, Issue 4, 1996, Pages 61-65

  Soden, Jerry M ^a,b,c,h   Hawkins, Charles F ^a,b,d,e,f,g  

^a SANDIA NATIONAL LABORATORIES   (United States)

^b UNIVERSITY OF NEW MEXICO   (United States)

^c KANSAS STATE UNIVERSITY   (United States)

^d UNIVERSITY OF FLORIDA   (United States)

^e NORTHEASTERN UNIVERSITY

^f UNIVERSITY OF MICHIGAN   (United States)

^g IEEE

^h SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COST EFFECTIVENESS; CURRENT DENSITY; DEFECTS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; SCANNING ELECTRON MICROSCOPY;

BUILT IN CURRENT SENSORS (BICS); NODE VOLTAGE WEAKENING;

INTEGRATED CIRCUIT TESTING;

EID: 0030399873     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.544537     Document Type: Review

References (21)

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