A low-resistance self-aligned T-shaped gate for high-performance sub-0.1-μm CMOS

IEEE Transactions on Electron Devices

Volumn 44, Issue 6, 1997, Pages 951-956

  Hisamoto, Digh ^a   Umeda, Kazunori ^a   Nakamura, Yoshitaka ^a   Kimura, ShiN'ichiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE; GATES (TRANSISTOR); MOS DEVICES; OSCILLATORS (ELECTRONIC); SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING; SEMICONDUCTOR GROWTH;

RING OSCILLATORS;

CMOS INTEGRATED CIRCUITS;

EID: 0031164495     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.585550     Document Type: Article

References (15)

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