On estimating bounds of the quiescent current for IDDQ testing

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 106-111

  Ferre, Antoni ^a   Figueras, Joan ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; CALCULATIONS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DEFECTS; ELECTRIC CURRENTS; ERROR DETECTION; ESTIMATION; HEURISTIC METHODS; LEAKAGE CURRENTS; LOGIC CIRCUITS; MONTE CARLO METHODS;

AUTOMATIC TEST PATTERN GENERATOR; LOGIC SIMULATOR; LOGIC TEST; QUIESCENT CURRENT;

INTEGRATED CIRCUIT TESTING;

EID: 0029700346     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)