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Volumn , Issue , 1996, Pages 41-44

Standard cell library characterization for setting current limits for IDDQ testing

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS;

EID: 0002018073     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IDDQ.1996.557810     Document Type: Conference Paper
Times cited : (7)

References (15)
  • 1
    • 0020596281 scopus 로고
    • Testing for bridging faults (shorts) in CMOS circuits
    • Miami Beach, FL, June
    • J. M. Acken, "Testing for Bridging Faults (Shorts) in CMOS Circuits," Proc. 20th DAC, Miami Beach, FL, June 1983, pp. 717-718.
    • (1983) Proc. 20th DAC , pp. 717-718
    • Acken, J.M.1
  • 2
    • 85068237860 scopus 로고
    • Current measurement data to demonstrate setting current limits in a complete IDDQ testing methodology
    • October
    • J. M. Acken and S. D. Millman, "Current Measurement Data to Demonstrate Setting Current Limits in A Complete IDDQ Testing Methodology", IDDQ Testing Workshop, October, 1995.
    • (1995) IDDQ Testing Workshop
    • Acken, J.M.1    Millman, S.D.2
  • 3
    • 0029517664 scopus 로고
    • The final barriers to widespread use of IDDQ testing
    • October, Washington, D.C.
    • J. M. Acken, "The Final Barriers to Widespread use of IDDQ Testing," Proc. Int. Test Conf, October 1995, Washington, D.C., pp. 300.
    • (1995) Proc. Int. Test Conf , pp. 300
    • Acken, J.M.1
  • 4
    • 0347391919 scopus 로고
    • Development of a class 1 qtag monitor
    • October, Washington, D.C.
    • K. Baker, A Bratt, A. Richardson, and A. Webers, "Development of a Class 1 QTAG Monitor," Proc. Int. Test Conf., October 1994, Washington, D.C., pp. 213-221.
    • (1994) Proc. Int. Test Conf. , pp. 213-221
    • Baker, K.1    Bratt, A.2    Richardson, A.3    Webers, A.4
  • 5
    • 0029488127 scopus 로고
    • Stuck-at faults, ppms rejects or what do the sia roadmaps say?
    • October, Washington, D.C.
    • K. Baker, "Stuck-at Faults, PPMs Rejects or ? What do the SIA Roadmaps say?" Proc. Int. Test Conf., October 1995, Washington, D.C., pp. 299.
    • (1995) Proc. Int. Test Conf. , pp. 299
    • Baker, K.1
  • 6
    • 0028016990 scopus 로고
    • Power analysis for semi-custom design
    • May 1-4, , San Diego, CA
    • B J. George, G. Yeap, M.G. Wloka, S.C. Tyler, and D. Gossain, "Power Analysis for Semi-Custom Design," Proc. CICC, May 1-4, 1994, San Diego, CA, pp. 249-252.
    • (1994) Proc. CICC , pp. 249-252
    • George, B.J.1    Yeap, G.2    Wloka, M.G.3    Tyler, S.C.4    Gossain, D.5
  • 7
    • 0020290502 scopus 로고
    • A new fault model and testing technique for CMOS devices
    • November
    • Y. K. Malaiya and S. Y. H. Su, "A New Fault Model and Testing Technique for CMOS Devices," Proc. Int.Test Conf, November 1982, pp. 25-34.
    • (1982) Proc. Int.Test Conf , pp. 25-34
    • Malaiya, Y.K.1    Su, S.Y.H.2
  • 8
    • 0023210701 scopus 로고
    • Realistic fault modeling for VLSI testing
    • Miami Beach, FL, June 28-July 1
    • W. Maly, "Realistic Fault Modeling for VLSI Testing," Proc. 24th DAC, Miami Beach, FL, June 28-July 1, 1987, pp. 173-180.
    • (1987) Proc. 24th DAC , pp. 173-180
    • Maly, W.1
  • 9
    • 0026960793 scopus 로고
    • IDDQ testing as a component of a test suite: The need for several fault coverage metrics
    • December
    • P. C. Maxwell and R. C. Aitken, "IDDQ Testing as a Component of a Test Suite: The Need for Several Fault Coverage Metrics," Jour, of Elec. Testing: Theory and Applications, Vol. 3, No. 4, December 1992, pp. 19-30.
    • (1992) Jour, of Elec. Testing: Theory and Applications , vol.3 , Issue.4 , pp. 19-30
    • Maxwell, P.C.1    Aitken, R.C.2
  • 11
    • 0041981521 scopus 로고
    • IDDQ testing in CMOS digital asics-putting it all together
    • September
    • R. Perry, "IDDQ Testing in CMOS Digital ASICs-Putting It All Together," Proc. Int. Test Conf, September 1992, pp. 151-157.
    • (1992) Proc. Int. Test Conf , pp. 151-157
    • Perry, R.1
  • 12
    • 0029489611 scopus 로고
    • IDDQ testing of CMOS opens: An experimental stud
    • October
    • A. D. Singh, H. Rasheed, and W. W. Weber, "IDDQ Testing of CMOS Opens: An Experimental Stud/', Proc. Int. Test Conf, October 1995, pp. 479489.
    • (1995) Proc. Int. Test Conf , pp. 479-489
    • Singh, A.D.1    Rasheed, H.2    Weber, W.W.3
  • 14
    • 0005989307 scopus 로고
    • Comparing stuck fault and current testing via CMOS test chip
    • April
    • T. Storey, W. Maly, J. Andrews, and M. Miske, "Comparing Stuck Fault and Current Testing via CMOS Test Chip," European Test Conf, April 1991.
    • (1991) European Test Conf
    • Storey, T.1    Maly, W.2    Andrews, J.3    Miske, M.4
  • 15
    • 0029511849 scopus 로고
    • Test quality: Required stuck-at fault coverage with the use of IDDQ testing
    • October, Washington, D.C.
    • R. Wantuck, "Test Quality: Required Stuck-At Fault Coverage with the use of IDDQ Testing," Proc. Int. Test Conf, October 1995, Washington, D.C., pp. 301.
    • (1995) Proc. Int. Test Conf , pp. 301
    • Wantuck, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.