Functional test generation for synchronous sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 7, 1996, Pages 831-843

  Srinivas, M K ^a,c   Jacob, James ^b   Agrawal, Vishwani D ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

^b RUTGERS UNIVERSITY   (United States)

^c LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; MATHEMATICAL MODELS; MATRIX ALGEBRA; VECTORS;

CUBE BASED TEST GENERATION METHOD; FINITE STATE MACHINE; PROGRAMMABLE GATE ARRAY; SYNCHRONOUS SEQUENTIAL CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 0030193155     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.503950     Document Type: Article

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