Complete Test Sets for Logic Functions

IEEE Transactions on Computers

Volumn C-22, Issue 11, 1973, Pages 1016-1020

  Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

Complete test sets; expanded truth table; fault detect; ing test sets; logic networks; multiple stuck at faults; restricted gate networks; stuck at faults; unate gate networks

Indexed keywords

LOGIC CIRCUITS;

EID: 0015681902     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1973.223638     Document Type: Article

References (8)

1. R. Betancourt, “Derivation of minimum test sets for unate logical circuits,” IEEE Trans. Comput., vol. C-20, pp. 1264–1269, Nov. 1971.
2. A. D. Friedman, “Fault detection in redundant circuits,” IEEE Trans. Electron. Comput., vol. EC-16, pp. 99–100, Feb. 1967.
3. S. M. Reddy, “Easily testable realizations for logic functions,” IEEE Trans. Comput., vol. C-21, pp. 1183–1188, Nov. 1972.
4. ――, “A design procedure for fault-locatable switching circuits,” IEEE Trans. Comput., vol. C-21, pp. 1421–1426, Dec. 1972.
5. A. Mukhopadhyay, “Unate cellular logic,” IEEE Trans. Comput., vol. C-18, pp. 114–121, Feb. 1969.
6. D. C. Bossen and S. S. Hong, “Cause-effect analysis of multiple fault detection in combinational network,” IEEE Trans. Comput., vol. C-20, pp. 1252–1258, Nov. 1971.
7. A. R. Klayton and A. K. Susskind, “An algebraic approach to fault detection,” presented at the 2nd Workshop on Fault Detection and Diagnosis in Digital System, Lehigh Univ., Bethlehem, Pa., Dec. 1971.
8. S. B. Akers, Jr., “Universal test sets for logic networks,” in Proc. 13th Annu. Switching and Automata Theory Symp., Oct. 1972, pp. 177-184.