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Volumn 8, Issue 2, 1989, Pages 181-189

Logic Verification Algorithms and Their Parallel Implementation

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING--ALGORITHMS; COMPUTER SYSTEMS, DIGITAL--PARALLEL PROCESSING; LOGIC CIRCUITS, COMBINATORIAL;

EID: 0024611364     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.21836     Document Type: Article
Times cited : (7)

References (12)
  • 3
    • 0015558526 scopus 로고
    • VERIFY: An algorithm to verify a computer design
    • J.P. Roth, “VERIFY: An algorithm to verify a computer design,” IBM Tech. Disc. Bull., vol. 15, pp. 2646–2648, 1973.
    • (1973) IBM Tech. Disc. Bull. , vol.15 , pp. 2646-2648
    • Roth, J.P.1
  • 4
    • 0017723564 scopus 로고
    • Hardware verification
    • J.P. Roth, “Hardware verification,” IEEE Trans. Comput., vol. C-26, pp. 1292–1294, 1977.
    • (1977) IEEE Trans. Comput. , vol.26 C , pp. 1292-1294
    • Roth, J.P.1
  • 5
    • 0016892385 scopus 로고
    • Automatic identification of equivalence points for Boolean logic verification
    • Jan.
    • W.E. Donath and H. Ofek, “Automatic identification of equivalence points for Boolean logic verification,” IBM Tech. Disc. Bull., vol. 18, pp. 2700–2703, Jan. 1976.
    • (1976) IBM Tech. Disc. Bull. , vol.18 , pp. 2700-2703
    • Donath, W.E.1    Ofek, H.2
  • 7
    • 0022219498 scopus 로고
    • Symbolic verification of MOS circuits
    • (Chapel Hill, NC). Dec.
    • R.E. Bryant, “Symbolic verification of MOS circuits,” in Proc. 1985 Chapel Hill Conf. VLSI (Chapel Hill, NC). Dec. 1985, pp. 419–438.
    • (1985) Proc. 1985 Chapel Hill Conf. VLSI , pp. 419-438
    • Bryant, R.E.1
  • 9
    • 0023536960 scopus 로고
    • The Boulder optimal logic design system
    • (Santa Clara, CA), Nov.
    • D. Bostick et al., “The Boulder optimal logic design system,” in Proc. Int. Conf. Computer-Aided Des. (Santa Clara, CA), Nov. 1987, pp. 62–65.
    • (1987) Proc. Int. Conf. Computer-Aided Des. , pp. 62-65
    • Bostick, D.1
  • 10
    • 0019543877 scopus 로고
    • An implicit enumeration algorithm to generate tests for combinational logic circuits
    • Mar.
    • P. Goel, “An implicit enumeration algorithm to generate tests for combinational logic circuits,” IEEE Trans. Comput., vol. C-30, pp. 215–222, Mar. 1981.
    • (1981) IEEE Trans. Comput. , vol.30 C , pp. 215-222
    • Goel, P.1
  • 11
    • 0002609165 scopus 로고
    • A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran
    • (Kyoto, Japan), June 5–7
    • F. Brglez and H. Fujiwara, “A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran,” in Proc. 1985 IEEE Int. Symp. Circuits Syst. (Kyoto, Japan), June 5–7, 1985.
    • (1985) Proc. 1985 IEEE Int. Symp. Circuits Syst.
    • Brglez, F.1    Fujiwara, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.