Mustang: State Assignment of Finite State Machines Targeting Multilevel Logic Implementations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 7, Issue 12, 1988, Pages 1290-1300

  Devadas, Srinivas ^a   Ma, Hi Keung ^a   Newton, A Richard ^a   SangiovannIVincentelli, A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING--ALGORITHMS; OPTIMIZATION; SWITCHING THEORY--STATE ASSIGNMENT;

FINITE STATE MACHINES; MULTIVALUED LOGIC CIRCUITS;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0024168714     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.16807     Document Type: Article

References (15)

1. D.B. Armstrong, “A programmed algorithm for assigning internal codes to sequential machines,” IRE Trans. Electron. Comput., vol. EC-11, pp. 466–472, Aug. 1962.
2. T.A. Dolotta and E.J. McCluskey, “The coding of internal states of Sequential machines,” IEEE Trans. Electron. Comput., vol. EC-13, pp. 549–562, Oct. 1964.
3. H.C. Torng, “An Algorithm for finding secondary assignments of synchronous sequential circuits,” IEEE Trans. Computers, vol. C-17, pp. 416–469, May 1968.
4. G.D. Micheli, A. SangiovannIVincentelli, and T. Villa, “Computer-aided synthesis of PLA-based finite state machines,” in Proc. Int. Conf. on Computer-Aided Design, Santa Clara, CA, November 1983, 154–156.
5. G.D. Micheli, R.K. Brayton, and A. SangiovannIVincentelli, “Optimal state assignment of finite state machines,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 269–285, July 1985.
6. A.J. Coppola, “An implementation of a state assignment heuristic,” in Proc. 23rd Design Automation Conf, Las Vegas, NV, July 1986.
7. G.D. Micheli, “Symbolic design of combinational and sequential logic circuts implemented by two-level macros,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 597–616, Oct. 1986.
8. G. Saucier, M.C. Depaulet, and P. Sicard, “ASYL: A rule-based system for controller synthesis,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 1088–1098, Nov. 1987.
9. C. Tseng et al., “A versatile finite state machine synthesizer,” in Proc. Int. Conf. on Computer-Aided Design, Santa Clara, CA, pp. 206–209, Nov. 1986.
10. R.K. Brayton and C.T. McMullen, “Synthesis and optimization of multistage logic,” Proc. ICCD, Oct. 1984.
11. R.K. Brayton, R. Rudell, A. SangiovannIVincentelli, and A. Wang, “MIS: A multiple level logic optimization system,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 000–0000, Nov. 1987.
12. K. Bartlett, G.D. Hachtel, A.J.D. Geus, and W. Cohen, “Synthesis and optimization of multilevel logic under timing constraints,” in Proc. Int. Conf. on Computer-Aided Design, Santa Clara, CA, pp. 290–292, Nov. 1985.
13. R.K. Brayton, C.T. McMullen, G.D. Hachtel, and A.L. SangiovannIVincentelli, Logic Minimization Algorithms for VLSI Synthesis. New York: Kluwer Academic, 1984.
14. G.D. Micheli and A. SangiovannIVincentelli, “Multiple constrained folding of programmable logic arrays: Theory and applications,” IEEE Trans. Computer-Aided Design, vol. CAD-2, July 1983.
15. R.L. Graham and H.O. Pollak, “On embedding graphs in squashed cubes,” in Graph Theory and Applications 303. New York: Springer Verlag, 1972.