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Journal of Electronic Testing

Volumn 1, Issue 1, 1990, Pages 7-13

Differential fault simulation for sequential circuits

(2) Cheng, Wu Tung a Yu, Meng Lin a

a LUCENT TECHNOLOGIES (United States)

Author keywords

fault simulation; sequential circuits; test generation

Indexed keywords

EID: 0009974019 PISSN: 09238174 EISSN: 15730727 Source Type: Journal
DOI: 10.1007/BF00134011 Document Type: Article

Times cited : (19)

References (22)

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11
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- W. Ke. S.C. Seth, and B.B. Bhattacharya, “A fast fault simulation algorithm for combinational circuits,” Intern. Conf. on Computer-Aided Design, November 1988, pp. 166–169.

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14
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- F. Brglez, “A fast fault grader: Analysis and applications,” Intern. Test Conf., November 1985, pp. 785–794.

15
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- M. Abramovici, P.R. Menon, and D.T. Miller, “Critical path tracing—An alternative to fault simulation,” 20th Design Automation Conf., June 1983, pp 214–220.

16
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- S.K. Jain and V.D. Agrawal, “STAFAN: An alternative to fault simulation,” 21st Design Automation Conf., June 1984, pp. 18–23.

17
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- W.-T. Cheng, “SPLIT circuit model to test generation,” 25th Design Automation Conf., June 1988, pp. 96–101.

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21
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22
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- S. Davidson and J.L. Lewandowski, “ESIM/AFS—A concurrent architectural level fault simulator,” Intern. Test Conf., November 1985, pp. 663–698.

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.