Functional test generation for sequential circuits

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1992, Pages 17-24

  Jacob, J ^a   Agrawal, V D ^b  

^a INDIAN INSTITUTE OF SCIENCE   (India)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ITERATIVE METHODS; LOGIC SYNTHESIS; SEQUENTIAL CIRCUITS; TESTING; TIMING CIRCUITS; VLSI CIRCUITS;

BENCHMARK CIRCUIT; COMBINATIONAL LOGIC; FAULT COVERAGES; FAULT PROPAGATION; FUNCTIONAL TEST GENERATION; MULTI-LEVEL IMPLEMENTATION; PROGRAMMABLE LOGIC ARRAY; TEST SEQUENCE;

COMPUTER CIRCUITS;

EID: 85066414158     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.1992.658015     Document Type: Conference Paper

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