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Volumn , Issue , 1992, Pages 238-245

Finite state machine testing based on growth and disappearance faults

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TOLERANCE;

EID: 33747859799     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FTCS.1992.243578     Document Type: Conference Paper
Times cited : (4)

References (20)
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  • 6
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  • 8
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    • U. Dave and J. H. Patel, "A Functional-level Test Generation Methodolog-using Two-level Representations, " Proc. 26th Design Automation Conference, pp. 722-725, 1989.
    • (1989) Proc. 26th Design Automation Conference , pp. 722-725
    • Dave, U.1    Patel, J.H.2
  • 10
    • 0026153304 scopus 로고
    • Test generation and verification for highly sequential circuits
    • May
    • A. Ghosh, S. Devadas, and A. R. Newton, "Test Generation and Verification for Highly Sequential Circuits, " IEEE Trans. on CAD, vol. 10, pp. 652-667, May 1991.
    • (1991) IEEE Trans. on CAD , vol.10 , pp. 652-667
    • Ghosh, A.1    Devadas, S.2    Newton, A.R.3
  • 11
  • 12
    • 85066414158 scopus 로고
    • Functional test generation for sequential circuits
    • January, Bangalore, India
    • J. Jacob and V. D. Agrawal, "Functional Test Generation for Sequential Circuits", Proc. 5th Inti. Conf. VLSI Design, Bangalore, India, pp 17-24, January 1992.
    • (1992) Proc. 5th Inti. Conf. VLSI Design , pp. 17-24
    • Jacob, J.1    Agrawal, V.D.2
  • 14
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    • January, Bangalore, India
    • J. Jacob and N. N. Biswas, "PLATES: An Efficient PLA Test Pattern Generator, " Proc. Third Int. Workshop on VLSI Design, Bangalore, India, pp. 147-154, January 1990.
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    • Jacob, J.1    Biswas, N.N.2
  • 15
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    • Logic verification algsrithms and their parallel implementation
    • February
    • H. K. T. Ma and S. Devadas, "Logic Verification algsrithms and their Parallel Implementation", IEEE Trans. on CAD, vol. 8, pp 181-188, February 1989.
    • (1989) IEEE Trans. on CAD , vol.8 , pp. 181-188
    • Ma, H.K.T.1    Devadas, S.2
  • 16
    • 0026175222 scopus 로고
    • On achieving a complete fault coverage for sequential machines using the transition fault model
    • I. Pomeranz and S M Reddy, "On Achieving a Complete Fault Coverage for Sequential Machines using the Transition Fault Model", Proc. Design Automation Conf, 1991, pp 341-346.
    • (1991) Proc. Design Automation Conf , pp. 341-346
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  • 17
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  • 18
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    • August
    • D. R. Schertz and G. Metze, "A New Representation for Faults in Combinational Digital Circuits"IEEE Trans. on Computers, vol. C-21, pp. 858-866, August 1972.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.