On test set preservation of retimed circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1995, Pages 176-182

  El Maleh, Aiman ^a   Marchok, Thomas ^a   Rajski, Janusz ^a   Maly, Wojciech ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FAULT CURRENTS; FLIP FLOP CIRCUITS; LOGIC GATES; OPTIMIZATION; SHIFT REGISTERS; TIMING CIRCUITS; VECTORS;

AUTOMATIC TEST PATTERN GENERATORS; FAULT COVERAGE; FAULT EFFICIENCY; RETIMED CIRCUITS; STUCK AT FAULT TEST SET;

SEQUENTIAL CIRCUITS;

EID: 0029226474     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/217474.217526     Document Type: Conference Paper

References (13)