CAWA: Coordinated warp scheduling and cache prioritization for critical warp acceleration of GPGPU workloads

Proceedings - International Symposium on Computer Architecture

Volumn 13-17-June-2015, Issue , 2015, Pages 515-527

  Lee, Shin Ying ^a   Arunkumar, Akhil ^a   Wu, Carole Jean ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; COMPUTER GRAPHICS EQUIPMENT; CRITICALITY (NUCLEAR FISSION); MEMORY ARCHITECTURE; PROGRAM PROCESSORS; SCHEDULING;

CHIP MULTIPROCESSOR; EVALUATION RESULTS; GENERAL PURPOSE GPU; GRAPHICS PROCESSING UNIT; IMPROVE PERFORMANCE; MEMORY ACCESS LATENCY; PARALLEL WORKLOADS; RESOURCE UTILIZATIONS;

WEAVING;

EID: 84960122845     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2749469.2750418     Document Type: Conference Paper

References (39)

1. A. Bakhoda, G. Yuan, W. W. L. Fung, H. Wong, and T. M. Aamodt, "Analyzing CUDA workloads using a detailed GPU simulator," in Proc. of the 2009 IEEE International Symposium on Analysis of Systems and Software (ISPASS'09), Boston, MA, USA, April 2009.
2. A. Bhattacharjee and M. Martonosi, "Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors," in Proc. of the 36th IEEE/ACM International Symposium on Computer Architecture (ISCA'09), Austin, TX, USA, June 2009.
3. K. D. Bois, S. Eyerman, J. B. Sartor, and L. Eeckhout, "Criticality stacks: Identifying critical threads in parallel programs using synchronization behavior," in Proc. of the 40th IEEE/ACM International Symposium on Computer Architecture (ISCA'13), Tel Aviv, Israel, June 2013.
4. M. Burtscher, R. Nasre, and K. Pingali, "A quantitative study of irregular programs on GPUs," in Proc. of the 2012 IEEE International Symposium on Workload Characterization (IISWC'12), San Diego, CA, USA, November 2012.
5. S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron, "Rodinia: A benchmark suite for heterogeneous computing," in Proc. of the 2009 IEEE International Symposium on Workload Characterization (IISWC'09), Austin, TX, USA, October 2009.
6. S. Che, J. W. Sheaffer, M. Boyer, L. G. Szafaryn, L. Wang, and K. Skadron, "A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads," in Proc. of the 2010 IEEE International Symposium on Workload Characterization (IISWC'10), Atlanta, GA, USA, December 2010.
7. X. Chen, L.-W. Chang, C. I. Rodrigues, J. Lv, and W. mei Hwu, "Adaptive cache management for energy-efficient GPU computing," in Proc. of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'14), Cambridge, UK, December 2014.
8. E. Ebrahimi, R. Miftakhutdinov, C. Fallin, C. J. Lee, J. A. Joao, O. Mutlu, and Y. N. Patt, "Parallel application memory scheduling," in Proc. of the 44th International Symposium on Microarchitecture (MICRO'11), Porto Alegre, Brazil, December 2011.
9. W. L. W. Fung and T. M. Aamodt, "Thread block compaction for efficient SIMT control flow," in Proc. of the 17th IEEE International Symposium on High Performance Computer Architecture (HPCA'11), San Antonio, TX, USA, February 2011.
10. W. L. W. Fung, I. Sham, G. Yuan, and T. M. Aamodt, "Dynamic warp formation and scheduling for efficient GPU control flow," in Proc. of the 37th IEEE/ACM International Symposium on Computer Architecture (ISCA'10), Saint-Malo, France, June 2010.
11. M. Gebhart, R. D. Johnson, D. Tarjan, S. W. Keckler, W. J. Dally, E. Lindoholm, and K. Skadron, "Energy-efficient mechanisms for managing thread context in throughput processors," in Proc. of the 38th IEEE/ACM International Symposium on Computer Architecture (ISCA'11), San Jose, CA, USA, June 2011.
12. A. Jaleel, K. B. Theobald, S. C. Steely, Jr., and J. Emer, "High performance cache replacement using re-reference interval prediction (RRIP)," in Proc. of the 37th IEEE/ACM International Symposium on Computer Architecture (ISCA'10), Saint-Malo, France, June 2010.
13. W. Jia, K. A. Shaw, and M. Martonosi, "Characterizing and improving the use of demand-fetched caches in GPUs," in Proc. of the 20th ACM International Conference on Supercomputing (ICS'12), Venice, Italy, June 2012.
14. W. Jia, K. A. Shaw, and M. Martonosi, "MRPB: memory request prioritization for massively parallel processors," in Proc. of the 20th IEEE International Symposium on High Performance Computer Architecture (HPCA'14), Orlando, FL, USA, February 2014.
15. A. Jog, O. Kayiran, A. K. Mishra, M. T. Kandemir, O. Mutlu, R. Iyer, and C. R. Das, "Orchestrated scheduling and prefetching for GPGPUs," in Proc. of the 40th IEEE/ACM International Symposium on Computer Architecture (ISCA'13), Tel-Aviv, Isreal, June 2013.
16. A. Jog, O. Kayiran, N. C. Nachiappan, A. K. Mishra, M. T. Kandemir, O. Mutlu, R. Iyer, and C. R. Das, "OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance," in Proc. of the 18th IEEE/ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'13), Houston, TX, USA, March 2013.
17. G. Keramidas, P. Petoumenos, and S. Kaxiras, "Cache replacement based on reuse-distance prediction," in Proc. of the 25th IEEE International Conference on Computer Design (ICCD'07), Lake Tahoe, CA, USA, October 2007.
18. S. Khan, Y. Tian, and D. Jimenez, "Sampling dead block prediction for last-level caches," in Proc. of the 43rd IEEE/ACM International Symposium on Microarchitecture (MICRO'10), Atlanta, GA, USA, December 2010.
19. A.-C. Lai, C. Fide, and B. Falsafi, "Dead-block prediction&dead-block correlating prefetchers," in Proc. of the 28th IEEE/ACM International Symposium on Computer Architecture (ISCA'01), 2001.
20. S.-Y. Lee and C.-J. Wu, "CAWS: Criticality-aware warp scheduling for GPGPU workloads," in Proc. of the 23rd IEEE/ACM International Conference on Parallel Architectures and Compilation (PACT'14), Edmonton, AB, Canada, August 2014.
21. S.-Y. Lee and C.-J. Wu, "Characterizing the latency hiding ability of GPUs," in Proc. of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'14) as Poster Abstract, Monterey, CA, USA, March 2014.
22. E. Lindholm, J. Nickolls, S. Oberman, and J. Montrym, "NVIDIA Tesla: A unified graphics and computing architecture," IEEE Micro, vol. 28, pp. 39-55, March 2008.
23. J. Meng, D. Tarjan, and K. Skadron, "Dynamic warp subdivision for integrated branch and memory divergence tolerance," in Proc. of the 37th IEEE/ACM International Symposium on Computer Architecture (ISCA'10), Saint-Malo, France, June 2010.
24. V. Narasiman, M. Shebanow, C. J. Lee, R. Miftakhutdinov, O. Mutlu, and Y. N. Patt, "Improving GPU performance via large warps and twolevel warp scheduling," in Proc. of the 44th International Symposium on Microarchitecture (MICRO'11), Porto Alegre, Brazil, December 2011.
25. NVIDIA, "PTX ISA," 2009. Available: http://www.nvidia.com/content/CUDA-ptx-isa-1.4.pdf
26. NVIDIA, "NVIDIA CUDA C programming guide v4.2," 2012. Available: http://developer.nvidia.com/nvidia-gpu-computing-documentation
27. NVIDIA, "NVIDIA GeForce GTX 980: Featuring Maxwell, the most advanced GPU ever made," September 2014.
28. M. A. O'Neil and M. Burtscher, "Microarchitectural performance characterization of irregular GPU kernels," in Proc. of the 2014 IEEE International Symposium on Workload Characterization (IISWC'14), Raleigh, NC, USA, October 2014.
29. M. K. Qureshi, A. Jaleel, Y. N. Patt, S. C. Steely Jr., and J. Emer, "Adaptive insertion policies for high performance caching," in Proc. of the 34th IEEE/ACM International Symposium on Computer Architecture (ISCA'07), San Diego, CA, USA, June 2007.
30. M. K. Qureshi, A. Jaleel, Y. N. Patt, S. C. Steely Jr., and J. Emer, "Setdueling-controlled adaptive insertion for high-performance caching," IEEE Micro, vol. 28, no. 1, pp. 91-98, January 2008.
31. M. K. Qureshi and Y. N. Patt, "Utility-based cache partitioning: A lowoverhead, high-performance, runtime mechanism to partition shared caches," in Proc. of the 39th IEEE/ACM International Symposium on Microarchitecture (MICRO'06), Orlando, FL, USA, December 2006.
32. M. Rhu and M. Erez, "The dual-path execution model for efficient GPU control flow," in Proc. of the 19th IEEE International Symposium on High Performance Computer Architecture (HPCA'13), Shenzhen, China, February 2013.
33. M. Rhu, M. Sullivan, J. Leng, and M. Erez, "A locality-aware memory hierarchy for energy-efficient GPU architecture," in Proc. of the 46th International Symposium on Microarchitecture (MICRO'13), Davis, CA, USA, December 2013.
34. T. G. Rogers, M. O'Connor, and T. M. Aamodt, "Cache-conscious wavefront scheduling," in Proc. of the 45th IEEE/ACM International Symposium on Microarchitecture (MICRO'12), Vancouver, BC, Canada, December 2012.
35. T. G. Rogers, M. O'Connor, and T. M. Aamodt, "Divergence-aware warp scheduling," in Proc. of the 46th IEEE/ACM International Symposium on Microarchitecture (MICRO'13), Davis, CA, USA, December 2013.
36. J. A. Stratton, C. Rodrigues, I.-J. Sung, N. Obeid, L.-W. Chang, N. Anssari, G. D. Liu, and W.-M. W. Hwu, "The Parboil technical report," in IMPACT Technical Report (IMPACT-12-01), University of Illinois Urbana-Champaign, Champaign, IL, USA, March 2012.
37. A. S. Vaidya, A. Shayesteh, D. H. Woo, R. Saharoy, and M. Azimi, "SIMD divergence optimization through intra-warp compaction," in Proc. of the IEEE/ACM 40th International Symposium on Computer Architecture (ISCA'13), Tel Aviv, Israel, June 2011.
38. C.-J. Wu, A. Jaleel, W. Hasenplaugh, M. Martonosi, S. C. Steely, Jr., and J. Emer, "SHiP: signature-based hit predictor for high performance caching," in Proc. of the 44th IEEE/ACM International Symposium on Microarchitecture (MICRO'11), Porto Alegre, Brazil, December 2011.
39. X. Xie, Y. Liang, G. Sun, and D. Chen, "An efficient compiler framework for cache bypassing on GPUs," in Proc. of the 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD'13), San Jose, CA, USA, November 2013.