MRPB: Memory request prioritization for massively parallel processors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2014, Pages 272-283

  Jia, Wenhao ^a   Shaw, Kelly A ^b   Martonosi, Margaret ^a  

^a PRINCETON UNIVERSITY   (United States)

^b UNIVERSITY OF RICHMOND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; PROGRAM PROCESSORS; SUPERCOMPUTERS;

CACHE MANAGEMENT TECHNIQUES; GPU PROGRAMMING; GRAPHICS PROCESSING UNITS; HARDWARE STRUCTURES; MASSIVELY PARALLEL PROCESSORS; MASSIVELY PARALLELS; MEMORY HIERARCHY; PERFORMANCE IMPACT;

CACHE MEMORY;

EID: 84903985058     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2014.6835938     Document Type: Conference Paper

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