SHiP: Signature-based hit predictor for high performance caching

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 430-441

  Wu, Carole Jean ^a   Jaleel, Aamer ^b   Hasenplaugh, Will ^b,c   Martonosi, Margaret ^a   Steely Jr , Simon C ^b   Emer, Joel ^b,c  

^a PRINCETON UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

replacement; reuse distance prediction; shared cache

Indexed keywords

APPLICATION PERFORMANCE; CACHE PERFORMANCE; HARDWARE OVERHEADS; MEMORY REGION; OFF-CHIP MEMORIES; PERFORMANCE GAIN; PROGRAM COUNTERS; REPLACEMENT; REPLACEMENT POLICY; REUSE DISTANCE; SHARED CACHE;

CACHE MEMORY; FORECASTING; MULTIPROGRAMMING; PROGRAM PROCESSORS; SHIPS;

VEHICLE PERFORMANCE;

EID: 84863389330     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155671     Document Type: Conference Paper

References (33)

1. S. Bansal and D. S. Modha. CAR: Clock with adaptive replacement. In Proc. of the 3rd USENIX Conference on File and Storage Technologies, 2004.
2. A. Basu, N. Kirman, M. Kirman, and M. Chaudhuri. Scavenger: A new last level cache architecture with global block priority. In Proc. of the 40th International Symposium on Microarchitecture, 2007.
3. L. A. Belady. A study of replacement algorithms for a virtual storage computer. In IBM Syst. J., volume 5, June 1966.
4. M. Chaudhuri. Pseudo-LIFO: the foundation of a new family of replacement policies for LLCs. In Proc. of the 42nd International Symposium on Microarchitecture, 2009.
5. H. Gao and C. Wilkerson. A dueling segmented LRU replacement algorithm with adaptive bypassing. In Proc. of the 1st JILP Workshop on Computer Architecture Competitions, 2010.
6. Z. Hu, S. Kaxiras, and M. Martonosi. Timekeeping in the memory system: Predicting and optimizing memory behavior. In Proc. of the 29th International Symposium on Computer Architecture, 2002.
7. Intel Core i7 Processors http://www.intel.com/products/processor/corei7/.
8. A. Jaleel, R. S. Cohn, C.-K. Luk, and B. Jacob. CMP$im: A Pin-based on-the-fly multi-core cache simulator. In Proc. of the 4th Workshop on Modeling, Benchmarking and Simulation, 2008.
9. A. Jaleel, W. Hasenplaugh, M. Qureshi, J. Sebot, S. C. Steely Jr., and J. Emer. Adaptive insertion policies for managing shared caches. In Proc. of the 17th International Conference on Parallel Architecture and Compilation Techniques, 2008.
10. A. Jaleel, K. B. Theobald, S. C. Steely Jr., and J. Emer. High performance cache replacement using re-reference interval prediction (RRIP). In Proc. of the 38th International Symposium on Computer Architecture, 2010.
11. S. Jiang and X. Zhang. LIRS: An efficient low inter-reference recency set replacement policy to improve buffer cache performance. In Proc. of the International Conference on Measurement and Modeling of Computer Systems, 2002.
12. JILP Workshop on computer architecture competitions http://jilp.org/jwac- 1/.
13. S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Proc. of the 28th International Symposium on Computer Architecture, 2001.
14. G. Keramidas, P. Petoumenos, and S. Kaxiras. Cache replacement based on reuse-distance prediction. In Proc. of the 25th International Conference on Computer Design, 2007.
15. S. M. Khan, D. A. Jiménez, D. Burger, and B. Falsafi. Using dead blocks as a virtual victim cache. In Proc. of the 19th International Conference on Parallel Architecture and Compilation Techniques, 2010.
16. S. M. Khan, Y. Tian, and D. A. Jiménez. Dead block replacement and bypass with a sampling predictor. In Proc. of the 43rd International Symposium on Microarchitecture, 2010.
17. M. Kharbutli and Y. Solihin. Counter-based cache replacement and bypassing algorithms. In IEEE Trans. Comput., volume 57, April 2008.
18. A. Lai, C. Fide, and B. Falsafi. Dead-block prediction & dead-block correlating prefetchers. In Proc. of the 28th International Symposium on Computer Architecture, 2001.
19. D. Lee, J. Choi, J. H. Kim, S. H. Noh, S. L. Min, Y. Cho, and C. S. Kim. LRFU: A spectrum of policies that subsumes that least recently used and least frequently used policies. In IEEE Trans. Comput., volume 50, December 2001.
20. H. Liu, M. Ferdman, J. Huh, and D. Burger. Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency. In Proc. of the 41st International Symposium on Microarchitecture, 2008.
21. G. Loh. Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy. In Proc. of the 42nd International Symposium on Microarchitecture, 2009.
22. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: Building customized program analysis tools with dynamic instrumentation. In Proc. of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2005.
23. R. Manikantan, K. Rajan, and R. Govindarajan. NUcache: An efficient multicore cache organization based on next-use distance. In Proc. of the 17th International Symposium on High Performance Computer Architecture, 2011.
24. N. Megiddo and D. S. Modha. A self-tuning low overhead replacement cache. In Proc. of the 2nd USENIX Conference on File and Storage Technologies, 2003.
25. H. Patil, R. Cohn, M. Charney, R. Kapoor, A. Sun, and A. Karunanidhi. Pinpointing representative portions of large Intel Itanium programs with dynamic instrumentation. In Proc. of the 37th International Symposium on Microarchitecture, 2004.
26. P. Petoumenos, G. Keramidas, and S. Kaxiras. Instruction-based reuse-distance prediction for effective cache management. In Proc. of the 9th International Conference on Systems, Architectures, Modeling and Simulation, 2009.
27. M. K. Qureshi, A. Jaleel, Y. N. Patt, S. C. Steely Jr., and J. Emer. Adaptive insertion policies for high performance caching. In Proc. of the 35th International Symposium on Computer Architecture, 2007.
28. K. Rajan and G. Ramaswamy. Emulating optimal replacement with a shepherd cache. In Proc. of the 40th International Symposium on Microarchitecture, 2007.
29. S. Srinath, O. Mutlu, H. Kim, and Y. N. Patt. Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers. In Proc. of the 13th International Symposium on High Performance Computer Architecture, 2007.
30. R. Subramanian, Y. Smaragdakis, and G. Loh. Adaptive caches: Effective shaping of cache behavior to workloads. In Proc. of the 39th International Symposium on Microarchitecture, 2006.
31. C.-J. Wu and M. Martonosi. Adaptive timekeeping replacement: Fine-grained capacity management for shared CMP caches. In ACM Trans. Archit. Code Optim., volume 8, February 2011.
32. Y. Xie and G. Loh. PIPP: Promotion/insertion pseudo-partitioning of multi-core shared caches. In Proc. of the 37th International Symposium on Computer Architecture, 2009.
33. T. Yeh and Y. N. Patt. Two-level adaptive training branch prediction. In Proc. of the 24th International Symposium on Microarchitecture, 1991.