Divergence-aware warp scheduling

MICRO 2013 - Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

Volumn , Issue , 2013, Pages 99-110

  Rogers, Timothy G ^a   O'Connor, Mike ^b   Aamodt, Tor M ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^b NVIDIA   (United States)

Author keywords

caches; divergence; GPU; scheduling

Indexed keywords

CACHES; DIVERGENCE; GPU; HARDWARE THREAD SCHEDULING; ON-LINE CHARACTERIZATION; PROACTIVE SCHEDULING; RUN-TIME INFORMATION; SPARSE MATRIX-VECTOR MULTIPLY;

CACHE MEMORY; COMPUTER ARCHITECTURE; ENERGY EFFICIENCY; FORECASTING; HARDWARE; PROGRAM PROCESSORS; SCHEDULING; WAVEFRONTS;

WEAVING;

EID: 84892547586     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2540708.2540718     Document Type: Conference Paper

References (37)

1. NVIDIA CUDA C Programming Guide v4.2, 2012.
2. T. M. Aamodt et al. GPGPU-Sim 3.x Manual. http://gpgpu-sim.org/manual/ index.php5/GPGPU-Sim-3.x-Manual, 2012.
3. A. Bakhoda et al. Analyzing CUDA Workloads Using a Detailed GPU Simulator. In ISPASS 2009, pages 163-174.
4. K. Barabash and E. Petrank. Tracing Garbage Collection on Highly Parallel Platforms. In ISMM 2010, pages 1-10.
5. R. Barrett et al. Templates for the Solution of Linear Systems: Building Blocks for Iterative Methods, 2nd Edition. SIAM, 1994.
6. N. Bell and M. Garland. Implementing sparse matrix-vector multiplication on throughput-oriented processors. In SC 2009.
7. S. Che et al. Rodinia: A Benchmark Suite for Heterogeneous Computing. In IISWC 2009, pages 44-54.
8. H.-Y. Cheng et al. Memory Latency Reduction via Thread Throttling. In MICRO-43, pages 53-64, 2010.
9. A. Danalis et al. The Scalable Heterogeneous Computing (SHOC) benchmark suite. In GPGPU 2010.
10. H. Esmaeilzadeh et al. Dark Silicon and the End of Multicore Scaling. In ISCA 2011, pages 365-376.
11. W. Fung and T. Aamodt. Thread Block Compaction for Efficient SIMT Control Flow. In HPCA 2011, pages 25-36.
12. W. W. L. Fung et al. Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. In MICRO-40.
13. M. Gebhart and D. R. Johnson et al. Energy-Efficient Mechanisms for Managing Thread Context in Throughput Processors. In ISCA 2011, pages 235-246.
14. Z. Guz et al. Many-Core vs. Many-Thread Machines: Stay Away From the Valley. Computer Architecture Letters, pages 25-28, jan. 2009.
15. T. H. Hetherington et al. Characterizing and Evaluating a Key-Value Store Application on Heterogeneous CPU-GPU Systems. In ISPASS 2012, pages 88-98.
16. S. Hong et al. Accelerating CUDA Graph Algorithms at Maximum Warp. In PPoPP 2011, pages 267-276.
17. A. Jaleel et al. CRUISE: Cache Replacement and Utility-Aware Scheduling. In ASPLOS 2012, pages 249-260.
18. A. Jaleel et al. High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP). In ISCA 2010, pages 60-71.
19. W. Jia, K. A. Shaw, and M. Martonosi. Characterizing and Improving the use of Demand-Fetched Caches in GPUs. In ICS 2012, pages 15-24.
20. A. Jog et al. OWL: Cooperative Thread Array Aware Scheduling Techniques for Improving GPGPU Performance. In ASPLOS 2013.
21. A. Jog et al. Orchestrated Scheduling and Prefetching for GPGPUs. In ISCA, 2013.
22. O. Kayiran et al. Neither More Nor Less: Optimizing Thread-level Parallelism for GPGPUs. In PACT 2013.
23. Khronos Group. OpenCL. http://www.khronos.org/opencl/.
24. N. B. Lakshminarayana and H. Kim. Effect of Instruction Fetch and Memory Scheduling on GPU Performance. In Workshop on Language, Compiler, and Architecture Support for GPGPU, 2010.
25. J. Lee, N. B. Lakshminarayana, H. Kim, and R. Vuduc. Many-Thread Aware Prefetching Mechanisms for GPGPU Applications. In MICRO-43, pages 213-224, 2010.
26. J. Leng et al. GPUWattch: Enabling Energy Optimizations in GPGPUs. In ISCA 2013.
27. E. Lindholm et al. NVIDIA Tesla: A Unified Graphics and Computing Architecture. Micro, IEEE, 28(2):39-55, March-April 2008.
28. M. Maas et al. How a Single Chip Causes Massive Power Bills GPUSimPow: A GPGPU Power Simulator. In ISPASS 2013.
29. J. Meng, D. Tarjan, and K. Skadron. Dynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance. In ISCA 2010, pages 235-246.
30. V. Narasiman et al. Improving GPU Performance via Large Warps and Two-Level Warp Scheduling. In MICRO-44, pages 308-317, 2011.
31. M. K. Qureshi et al. Adaptive Insertion Policies for High Performance Caching. In ISCA 2007, pages 381-391.
32. T. G. Rogers. CCWS Simulation Infrastructure. http://www.ece.ubc.ca/ ~tgrogers/ccws.html, 2013.
33. T. G. Rogers, M. O'Connor, and T. M. Aamodt. Cache-Conscious Wavefront Scheduling. In MICRO-45, 2012.
34. S. Rul et al. An Experimental Study on Performance Portability of OpenCL Kernels. In Application Accelerators in High Performance Computing, 2010.
35. G. S. Sohi, S. E. Breach, and T. N. Vijaykumar. Multiscalar Processors. In ISCA 1995.
36. D. Spoonhower, G. Blelloch, and R. Harper. Using Page Residency to Balance Tradeoffs in Tracing Garbage Collection. In Proc. of Int'l Conf. on Virtual Execution Environments (VEE 2005), pages 57-67.
37. S. Wilton and N. Jouppi. CACTI: An Enhanced Cache Access and Cycle Time Model. Solid-State Circuits, IEEE Journal of, 31(5):677-688, May 1996.