Neural acceleration for GPU throughput processors

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 05-09-December-2015, Issue , 2015, Pages 482-493

  Yazdanbakhsh, Amir ^a   Park, Jongse ^a   Sharma, Hardik ^a   Lotfi Kamran, Pejman ^b   Esmaeilzadeh, Hadi ^a  

^a Georgia Institute of Technology   (United States)

^b Institute for Research in Fundamental Sciences (IPM)   (United States)

Author keywords

approximate computing; GPU; neural processing unit

Indexed keywords

ACCELERATION; BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; EMBEDDED SYSTEMS; IMAGE CODING; PROGRAM PROCESSORS; QUALITY CONTROL;

APPROXIMATE COMPUTING; APPROXIMATION TECHNIQUES; CYCLE-ACCURATE SIMULATION; DATA-LEVEL PARALLELISM; GRAPHICS PROCESSING UNITS; HARDWARE OVERHEADS; MANY-CORE ACCELERATORS; NEURAL-PROCESSING;

COMPUTER HARDWARE;

EID: 84959896262     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2830772.2830810     Document Type: Conference Paper

References (59)

1. H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger, "Dark silicon and the end of multicore scaling, " in ISCA, 2011.
2. N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki, "To-ward dark silicon in servers, " IEEE Micro, 2011.
3. G. Venkatesh, J. Sampson, N. Goulding, S. Garcia, V. Bryksin, J. Lugo-Martinez, S. Swanson, and M. B. Taylor, "Conservation cores: Reducing the energy of mature computations, " in ASP-LOS, 2010.
4. J. Gantz and D. Reinsel, "Extracting value from chaos. " http: //www. emc. com.
5. GeForce 400 series. " http: //en. wikipedia. org, 2015.
6. M. Samadi, J. Lee, D. A. Jamshidi, A. Hormati, and S. Mahlke, "SAGE: self-tuning approximation for graphics engines, " in MI-CRO, 2013.
7. M. Samadi, D. A. Jamshidi, J. Lee, and S. Mahlke, "Paraprox: Pattern-based approximation for data parallel applications, " in ASPLOS, 2014.
8. J.-M. Arnau, J.-M. Parcerisa, and P. Xekalakis, "Eliminating re-dundant fragment shader executions on a mobile GPU via hard-ware memoization, " ISCA, 2014.
9. J. Sartori and R. Kumar, "Branch and data herding: Reducing control and memory divergence for error-tolerant GPU applica-tions, " Multimedia, IEEE Transactions on, 2013.
10. H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger, "Neu-ral acceleration for general-purpose approximate programs, " in MICRO, 2012.
11. R. S. Amant, A. Yazdanbakhsh, J. Park, B. Thwaites, H. Es-maeilzadeh, A. Hassibi, L. Ceze, and D. Burger, "General-purpose code acceleration with limited-precision analog compu-tation, " in ISCA, 2014.
12. B. Grigorian, N. Farahpour, and G. Reinman, "BRAINIAC: Bringing reliable accuracy into neurally-implemented approxi-mate computing, " in HPCA, 2015.
13. T. Moreau, M. Wyse, J. Nelson, A. Sampson, H. Esmaeilzadeh, L. Ceze, and M. Oskin, "SNNAP: Approximate computing on programmable socs via neural acceleration, " in HPCA, 2015.
14. L. McAfee and K. Olukotun, "EMEURO: A framework for gen-erating multi-purpose accelerators via deep learning, " in CGO, 2015.
15. B. Grigorian and G. Reinman, "Accelerating divergent applica-tions on SIMD architectures using neural networks, " in ICCD, 2014.
16. A. Sampson, W. Dietl, E. Fortuna, D. Gnanapragasam, L. Ceze, and D. Grossman, "EnerJ: Approximate data types for safe and general low-power computation, " in PLDI, 2011.
17. M. Carbin, S. Misailovic, and M. C. Rinard, "Verifying quanti-tative reliability for programs that execute on unreliable hard-ware, " in OOPSLA, 2013.
18. J. Park, H. Esmaeilzadeh, X. Zhang, M. Naik, and W. Harris, "Flexjava: Language support for safe and modular approximate programming, " in FSE, 2015.
19. A. Yazdanbakhsh, D. Mahajan, B. Thwaites, J. Park, A. Na-gendrakumar, S. Sethuraman, K. Ramkrishnan, N. Ravindran, R. Jariwala, A. Rahimi, H. Esmaeilzadeh, and K. Bazargan, "Axilog: Language support for approximate hardware design, " in DATE, 2015.
20. J. P. Banning, "An efficient way to find the side effects of proce-dure calls and the aliases of variables, " in POPL, 1979.
21. D. E. Rumelhart, G. E. Hinton, and R. J. Williams, "Learning internal representations by error propagation, " in PDP, 1986.
22. Whitepaper: NVIDIA Fermi. " http: //www. nvidia. com.
23. NVIDIA corporation. NVIDIA CUDA SDK code samples. " http: //www. nvidia. com.
24. S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron, "Rodinia: A benchmark suite for heterogeneous computing, " in IISWC, 2009.
25. jMonkeyEngine, 2015.
26. O. A. Aguilar and J. C. Huegel, "Inverse kinematics solution for robotic manipulators using a cuda-based parallel genetic algo-rithm, " AAI, 2011.
27. M. Creel and M. Zubair, "A high performance implementation of likelihood estimators on gpus, " in CES, 2013.
28. H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger, "Archi-tecture support for disciplined approximate programming, " in ASPLOS, 2012.
29. W. Baek and T. M. Chilimbi, "Green: A framework for support-ing energy-conscious programming using controlled approxima-tion, " in PLDI, 2010.
30. S. Sidiroglou-Douskos, S. Misailovic, H. Hoffmann, and M. Ri-nard, "Managing performance vs. accuracy trade-offs with loop perforation, " in FSE, 2011.
31. A. Bakhoda, G. Yuan, W. Fung, H. Wong, and T. Aamodt, "An-alyzing cuda workloads using a detailed GPU simulator, " in IS-PASS, 2009.
32. J. Leng, T. Hetherington, A. ElTantawy, S. Gilani, N. S. Kim, T. M. Aamodt, and V. J. Reddi, "GPUWattch: Enabling energy optimizations in gpgpus, " in ISCA, 2013.
33. S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, "McPAT: An integrated power, area, and tim-ing modeling framework for multicore and manycore architec-tures, " in MICRO, 2009.
34. N. Muralimanohar, R. Balasubramonian, and N. Jouppi, "Op-timizing NUCA organizations and wiring alternatives for large caches with CACTI 6. 0, " in MICRO, 2007.
35. T. G. Rogers, M. O'Connor, and T. M. Aamodt, "Cache-conscious wavefront scheduling, " in MICRO, 2012.
36. S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens, "Memory access scheduling, " Archit. News, 2000.
37. N. Vijaykumar, G. Pekhimenko, A. Jog, A. Bhowmick, R. Ausavarungnirun, C. Das, M. Kandemir, T. C. Mowry, and O. Mutlu, "A case for core-assisted bottleneck acceleration in gpus: Enabling efficient data compression, " in ISCA, 2015.
38. S. Liu, K. Pattabiraman, T. Moscibroda, and B. G. Zorn, "Flikker: Saving refresh-power in mobile devices through crit-ical data partitioning, " in ASPLOS, 2011.
39. A. Sampson, J. Nelson, K. Strauss, and L. Ceze, "Approximate storage in solid-state memories, " in MICRO, 2013.
40. L. N. Chakrapani, B. E. S. Akgul, S. Cheemalavagu, P. Kork-maz, K. V. Palem, and B. Seshasayee, "Ultra-efficient (embed-ded) SOC architectures based on probabilistic CMOS (PCMOS) technology, " in DATE, 2006.
41. L. Leem, H. Cho, J. Bau, Q. A. Jacobson, and S. Mitra, "ERSA: Error resilient system architecture for probabilistic applications, " in DATE, 2010.
42. S. Misailovic, S. Sidiroglou, H. Hoffman, and M. Rinard, "Quality of service profiling, " in ICSE, 2010.
43. M. Rinard, H. Hoffmann, S. Misailovic, and S. Sidiroglou, "Pat-terns and statistical analysis for understanding reduced resource computing, " in Onward!, 2010.
44. J. Ansel, C. Chan, Y. L. Wong, M. Olszewski, Q. Zhao, A. Edel-man, and S. Amarasinghe, "Petabricks: A language and compiler for algorithmic choice, " in PLDI, 2009.
45. C. Alvarez, J. Corbal, and M. Valero, "Fuzzy memoization for floating-point multimedia applications, " IEEE Trans. Comput., 2005.
46. M. de Kruijf, S. Nomura, and K. Sankaralingam, "Relax: An ar-chitectural framework for software recovery of hardware faults, " in ISCA, 2010.
47. X. Li and D. Yeung, "Application-level correctness and its impact on fault tolerance, " in HPCA, 2007.
48. X. Li and D. Yeung, "Exploiting application-level correctness for low-cost fault tolerance, " J. Instruction-Level Parallelism, 2008.
49. M. de Kruijf and K. Sankaralingam, "Exploring the synergy of emerging workloads and silicon reliability trends, " in SELSE, 2009.
50. Y. Fang, H. Li, and X. Li, "A fault criticality evaluation frame-work of digital systems for error tolerant video applications, " in ATS, 2011.
51. S. Venkataramani, V. K. Chippa, S. T. Chakradhar, K. Roy, and A. Raghunathan, "Quality programmable vector processors for approximate computing, " in MICRO, 2013.
52. A. Ranjan, A. Raha, S. Venkataramani, K. Roy, and A. Raghu-nathan, "ASLAN: Synthesis of approximate sequential circuits, " in DATE, 2014.
53. S. Venkataramani, A. Sabne, V. Kozhikkottu, K. Roy, and A. Raghunathan, "SALSA: Systematic logic synthesis of approx-imate circuits, " in DAC, 2012.
54. J. Miao, A. Gerstlauer, and M. Orshansky, "Approximate logic synthesis under general error magnitude and frequency con-straints, " in ICCAD, 2013.
55. K. Nepal, Y. Li, R. I. Bahar, and S. Reda, "ABACUS: A tech-nique for automated behavioral synthesis of approximate com-puting circuits, " in DATE, 2014.
56. A. Lingamneni, C. Enz, K. Palem, and C. Piguet, "Synthesizing parsimonious inexact circuits through probabilistic design tech-niques, " ACM Trans. Embed. Comput. Syst., 2013.
57. A. Lingamneni, K. K. Muntimadugu, C. Enz, R. M. Karp, K. V. Palem, and C. Piguet, "Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling, " in CF, 2012.
58. B. Belhadj, A. Joubert, Z. Li, R. Heliot, and O. Temam, "Con-tinuous real-world inputs can open up alternative accelerator de-signs, " in ISCA, 2013.
59. Z. Du, A. Lingamneni, Y. Chen, K. Palem, O. Temam, and C. Wu, "Leveraging the error resilience of machine-learning ap-plications for designing highly energy efficient accelerators, " in ASP-DAC, 2014.