ASLAN: Synthesis of approximate sequential circuits

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2014, Pages

  Ranjan, Ashish ^a   Raha, Arnab ^a   Venkataramani, Swagath ^a   Roy, Kaushik ^a   Raghunathan, Anand ^a  

^a Purdue University   (United States)

Author keywords

Approximate Circuits; Approximate Computing; Logic Synthesis; Low Power Design; Sequential circuits

Indexed keywords

BENCHMARKING; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY CONSERVATION; HARDWARE; ITERATIVE METHODS; MOTION PICTURE EXPERTS GROUP STANDARDS; SEQUENTIAL CIRCUITS; VIRTUAL ADDRESSES;

APPROXIMATE COMPUTING; COMBINATIONAL BLOCKS; COMBINATIONAL LOGIC BLOCKS; FORMAL VERIFICATIONS; HARDWARE IMPLEMENTATIONS; LOGIC SYNTHESIS; LOW-POWER DESIGN; QUALITY CONSTRAINTS;

LOW POWER ELECTRONICS;

EID: 84903843071     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/DATE2014.377     Document Type: Conference Paper

References (29)

1. M. A. Breuer. Multi-media applications and imprecise computation. In Proc. Euromicro Conf. on Digital System Design, pages 2-7, Sept. 2005.
2. S. T. Chakradhar and A. Raghunathan. Best-effort computing: Rethinking parallel software and hardware. In Proc. DAC, pages 865-870, June 2010.
3. R. Hegde and N. R. Shanbhag. Energy-efficient signal processing via algorithmic noise-tolerance. In Proc. ISLPED, pages 30-35, 1999.
4. K. Palem et. al. Sustaining moore's law in embedded computing through probabilistic and approximate design: Retrospects and prospects. In Proc. CASES, pages 1-10, 2009.
5. P. K. Krause and I. Polian. Adaptive voltage over-scaling for resilient applications. In Proc. DATE, pages 1-6, March 2011.
6. D. Shin and S. K. Gupta. Approximate logic synthesis for error tolerant applications. In Proc. DATE, pages 957-960, Mar. 2010.
7. D. Shin and S. K. Gupta. A new circuit simplification method for error tolerant applications. In Proc. DATE, Mar. 2011.
8. V. Gupta et. al. IMPACT: Imprecise adders for low-power approximate computing. In Proc. ISLPED 2011, pages 409-414, Aug. 2011.
9. A. Lingamneni K. Palem et. al. Energy parsimonious circuit design through probabilistic pruning. In Proc. DATE, Mar. 2011.
10. S. Venkataramani et. al. Salsa: systematic logic synthesis of approximate circuits. In Proc. DAC, pages 796-801, 2012.
11. S. Venkataramani et. al. Substitute-and-simplify: A unified design paradigm for approximate and quality configurable circuits. In Proc. DATE, pages 1367-1372, 2013.
12. D. Shin and S. K. Gupta. A re-design technique for datapath modules in error tolerant applications. In Proc. ATS, pages 431-437, Nov. 2008.
13. A. B. Kahng and S. Kang. Accuracy-configurable adder for approximate arithmetic designs. In Proc. DAC, pages 820-825, 2012.
14. M. Olivieri et. al. Analysis and implementation of a novel leading zero anticipation algorithm for floating-point arithmetic units. Circuits and Systems II: Express Briefs, IEEE Trans. on, 54(8):685-689, Aug. 2007.
15. P. Kulkarni et. al. Trading accuracy for power with an underdesigned multiplier architecture. In Proc. VLSI Design, pages 346-351, Jan. 2011.
16. N. Banerjee et al. Process variation tolerant low power dct architecture. In Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07, pages 1-6, 2007.
17. K. Lengwehasatit et al. Scalable variable complexity approximate forward dct. Circuits and Systems for Video Technology, IEEE Transactions on, 14(11):1236-1248, 2004.
18. O. Grumberg E. Clarke and D. Peled. Model Checking, MIT Press. 1999.
19. Z. Manna and A. Pnueli. The Temporal Logic of Reactive and Concurrent Systems, Springer-Verlag. 1992.
20. R. Venkatesan et. al. MACACO: Modeling and analysis of circuits for approximate computing. In Proc. ICCAD, pages 667-673, Nov. 2011.
21. J. Huang J. Lach et. al. A methodology for energy-quality tradeoff using imprecise hardware. In Proc. DAC, pages 504-509, 2012.
22. Z. Kedemi et. al. Optimizing energy to minimize errors in dataflow graph using approximate adders. In CASES, pages 177-186, 2010.
23. Design Compiler, Synopsys Inc.
24. P. Jamieson et. al. Odin II-An Open-source Verilog HDL Synthesis tool for CAD Research. In Proc. FCCM, pages 149-156, 2010.
25. ABC: A System for Sequential Synthesis and Verification, Release 130314. http://www.eecs.berkeley.edu/alanmi/abc/.
26. Verilog2CNF,"http://web.eecs.umich.edu/valeria/teaching/eecs578 F09 old".
27. Minisat,"http://minisat.se/ ".
28. http://media.xiph.org/video/derf/.
29. S. Venkataramani et. al. Quality-programmable vector processors for approximate computing. In Proc. MICRO, pages 1-12, 2013.