Leveraging the error resilience of machine-learning applications for designing highly energy efficient accelerators

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2014, Pages 201-206

  Du, Zidong ^a   Palem, Krishna ^b   Lingamneni, Avinash ^b   Temam, Olivier ^c   Chen, Yunji ^a   Wu, Chengyong ^a  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

^b RICE UNIVERSITY   (United States)

^c INRIA   (France)

Author keywords

[No Author keywords available]

Indexed keywords

65-NM TECHNOLOGIES; COMPUTING SYSTEM; ENERGY EFFICIENT; ERROR RESILIENCE; HETEROGENEOUS MULTICORE; MACHINE-LEARNING; REDUCING ENERGY CONSUMPTION; RESOURCE SAVINGS;

COMPUTER AIDED DESIGN; ENERGY EFFICIENCY; ENERGY UTILIZATION; MEAN SQUARE ERROR;

NEURAL NETWORKS;

EID: 84897884384     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2014.6742890     Document Type: Conference Paper

References (25)

1. A. Lingamneni et al. Improving energy gains of inexact DSP hardware through reciprocative error compensation. in the 50th Design Automation Conference, pages 20:1-20:8, June 2013.
2. A. Lingamneni et al. Synthesizing parsimonious inexact circuits through probabilistic design techniques. in the ACM Transactions on Embedded Computing Systems, 12(2s):93:1-93:26, May 2013.
3. A. Asuncion and D. J. Newman. {UCI} Machine Learning Repository, 2007.
4. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. In International Conference on Parallel Architectures and Compilation Techniques, New York, New York, USA, 2008. ACM Press.
5. T. Chen, Y. Chen, M. Duranton, Q. Guo, A. Hashmi, M. Lipasti, A. Nere, S. Qiu, M. Sebag, and O. Temam. BenchNN: On the Broad Potential Application Scope of Hardware Neural Network Accelerators. In International Symposium on Workload Characterization, 2012.
6. D Shin et al. Approximate logic synthesis for error tolerant applications. in the proc. of DATE, pages 957-960, 2010.
7. P. Dubey. Recognition, Mining and Synthesis Moves Computers to the Era of Tera. Technology@Intel Magazine, 9(2):1-10, 2005.
8. H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger. Architecture support for disciplined approximate programming. In T. Harris and M. L. Scott, editors, ASPLOS, pages 301-312. ACM, 2012.
9. H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger. Neural Acceleration for General-Purpose Approximate Programs. In International Symposium on Microarchitecture, 2012.
10. G Venkatesh et al. Conservation Cores: Reducing the Energy of Mature Computations. in proc. of the Architectural Support for Programming Languages and Operating Systems, pages 205-218, March 2010.
11. J. George, B. Marr, B. E. S. Akgul, and K. V. Palem. Probabilistic arithmetic and energy efficient embedded signal processing. In proc. of IEEE/ACM CASES, pages 158-168, 2006.
12. S. Haykin. Neural Networks. Prentice Hall Intl, London, UK, 2nd edition, 1999.
13. K Palem et al. What to do about the end of moore's law, probably! in the 49th Annual Design Automation Conference, pages 924-929, 2012.
14. E. J. King and E. E. Swartzlander Jr. Data-dependent truncation scheme for parallel multipliers. In Signals, Systems & Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on, volume 2, pages 1178-1182. IEEE, 1997.
15. H. Larochelle, D. Erhan, A. Courville, J. Bergstra, and Y. Bengio. An empirical evaluation of deep architectures on problems with many factors of variation. In International Conference on Machine Learning, pages 473-480, New York, New York, USA, 2007. ACM Press.
16. Y. LeCun, L. Bottou, Y. Bengio, and P. Haffner. Gradient-Based Learning Applied to Document Recognition. Proceedings of the IEEE, 11(86):2278-2324, 1998.
17. Lingamneni et al. Energy parsimonious circuit design through probabilistic pruning. in proc. of DATE, pages 764-769, Mar. 2011.
18. Lingamneni et al. Parsimonious circuit design for error-tolerant applications through probabilistic logic minimization. in the proc. of the PATMOS, pages 204-213, 2011.
19. H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas. Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(4):850-862, Apr. 2010.
20. M. Muller. Dark Silicon and the Internet. In EE Times "Designing with ARM" virtual conference, 2010.
21. P Merolla et al. A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm. In IEEE Custom Integrated Circuits Conference, pages 1-4. IEEE, Sept. 2011.
22. K. V. Palem. Energy aware algorithm design via probabilistic computing: From algorithms and models to Moore's law and novel (semiconductor) devices. In proc. of CASES, pages 113-116, 2003.
23. M. Stojilovic, D. Novo, L. Saranovac, P. Brisk, and P. Ienne. Selective flexibility: Breaking the rigidity of datapath merging. in proc. of DATE, pages 1543-1548, march 2012.
24. O. Temam. A Defect-Tolerant Accelerator for Emerging High-Performance Applications. In International Symposium on Computer Architecture, Portland, Oregon, 2012.
25. Z. M. Kedem et al. Optimizing energy to minimize errors in dataflow graphs using approximate adders. In in proc. of CASES, pages 177-186, 2010.