Approximate logic synthesis under general error magnitude and frequency constraints

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2013, Pages 779-786

  Miao, Jin ^a   Gerstlauer, Andreas ^a   Orshansky, Michael ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATE LOGIC; BOOLEAN RELATIONS; DEVIATION MEASURES; FREQUENCY CONSTRAINT; FREQUENCY OF ERROR; MINIMIZATION PROBLEMS; MULTIPLIER BLOCKS; SYNTHESIS PROBLEMS;

BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; HEURISTIC ALGORITHMS; ITERATIVE METHODS;

PROBLEM SOLVING;

EID: 84893368533     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2013.6691202     Document Type: Conference Paper

References (23)

1. P. Albicocco, G. C. Cardarilli, A. Nannarelli, M. Petricca, and M. Re. Imprecise arithmetic for low power image processing. In Signals, Systems and Computers (ASILOMAR), 2012.
2. D. Baneres, J. Cortadella, and M. Kishinevsky. A recursive paradigm to solve boolean relations. In DAC, 2004.
3. R. Brayton and F. Somenzi. An exact minimizer for boolean relations. In ICCAD, 1989.
4. L. Chakrapani and K. Palem. A probabilistic boolean logic for energy efficient circuit and system design. In ASP-DAC, 2010.
5. V. Chippa, A. Raghunathan, K. Roy, and S. Chakradhar. Dynamic effort scaling: Managing the quality-efficiency tradeoff. DAC, 2011.
6. A. Ghosh, S. Devadas, and A. Newton. Heuristic minimization of boolean relations using testing techniques. In ICCD, 1990.
7. V. Gupta, D. Mohapatra, S. P. Park, A. Raghunathan, and K. Roy. IMPACT: imprecise adders for low-power approximate computing. In ISLPED, 2011.
8. K. He, A. Gerstlauer, and M. Orshansky. Controlled timing-error acceptance for low energy idct design. In DATE, 2011.
9. R. Hegde and N. Shanbhag. Soft digital signal processing. TVLSI01.
10. S.-W. Jeong and F. Somenzi. A new algorithm for the binate covering problem and its application to the minimization of boolean relations. In ICCAD, 1992.
11. F. Kurdahi, A. Eltawil, K. Yi, S. Cheng, and A. Khajeh. Low-power multimedia system design by aggressive voltage scaling. TVLSI10.
12. B. Lin and F. Somenzi. Minimization of symbolic relations. In ICCAD90.
13. A. Lingamneni, C. Enz, J. L. Nagel, K. Palem, and C. Piguet. Energy parsimonious circuit design through probabilistic pruning. In DATE2011.
14. S.-L. Lu. Speeding up processing with approximation circuits. Computer, 2004.
15. P. McGeer, J. Sanghavi, R. Brayton, and A. Vincentelli. Espressosignature: A new exact minimizer for logic functions. In DAC, 1993.
16. J. Miao, K. He, A. Gerstlauer, and M. Orshansky. Modeling and synthesis of quality-energy optimal approximate adders. In ICCAD12.
17. G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill Higher Education, 1994.
18. S. H. Nawab, A. V. Oppenheim, A. P. Chandrakasan, J. M. Winograd, and J. T. Ludwig. Approximate signal processing. VLSI Signal Processing, 15, 1997.
19. D. Shin and S. K. Gupta. Approximate logic synthesis for error tolerant applications. In DATE, 2010.
20. S. Venkataramani, A. Sabne, V. Kozhikkottu, K. Roy, and A. Raghunathan. Salsa: systematic logic synthesis of approximate circuits. In DAC, 2012.
21. Y. Watanabe and R. Brayton. Heuristic minimization of multiplevalued relations. TCAD, 1993.
22. T. Xanthopoulos and A. Chandrakasan. A low-power dct core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization. J. Solid-State Circuits, 2000.
23. N. Zhu, W. L. Goh, W. Zhang, K. S. Yeo, and Z. H. Kong. Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. TVLSI, 2010.