DimNoC: A dim silicon approach towards power-efficient on-chIP network

Proceedings - Design Automation Conference

Volumn 2015-July, Issue , 2015, Pages

  Zhan, Jia ^a   Ouyang, Jin ^b   Ge, Fen ^c   Zhao, Jishen ^d   Xie, Yuan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NVIDIA   (United States)

^c NANJING UNIVERSITY OF AERONAUTICS AND ASTRONAUTICS   (China)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Dark Silicon; Network on ChIP; STT RAM

Indexed keywords

COMPUTER AIDED DESIGN; ENERGY CONSERVATION; NETWORK ARCHITECTURE; PRODUCT DESIGN; ROUTERS; SERVERS; SILICON; STATIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; RANDOM ACCESS STORAGE; VLSI CIRCUITS;

BUFFER ARCHITECTURE; DARK SILICONS; ENERGY DELAY PRODUCT; MEMORY TECHNOLOGY; NETWORK-ON-CHIP(NOC); ON-CHIP NETWORKS; POWER DENSITIES; STT RAMS;

NETWORK-ON-CHIP;

EID: 84944088561     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2744769.2744824     Document Type: Conference Paper

References (29)

1. N. Agarwal, T. Krishna, L.-S. Peh, and N. K. Jha. GARNET: A detailed on-chIP network model inside a full-system simulator. In ISPASS, pages 33-42, 2009.
2. D. U. Becker. Efficient microarchitecture for network-on-chIP routers. PhD thesis, Stanford University, 2012.
3. S. Bell et al. Tile64-processor: A 64-core soc with mesh interconnect. In ISSCC, pages 88-598, 2008.
4. L. Chen and T. M. Pinkston. Nord: Node-router decoupling for effective power-gating of on-chIP routers. In MICRO-45, pages 270-281, 2012.
5. K. C. Chun et al. A scaling roadmap and performance evaluation of in-plane and perpendicular MTJ based STT-MRAMs for high-density cache memory. IEEE Journal of Solid-State Circuits, 48(2):598-610, 2013.
6. R. Das, S. Narayanasamy, S. Satpathy, and R. Dreslinski. Catnap: Energy proportional multIPle network-on-chIP. In ISCA, pages 320-331, 2013.
7. X. Dong, C. Xu, Y. Xie, and N. P. Jouppi. Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory. TCAD, 31(7):994-1007, 2012.
8. H. Esmaeilzadeh et al. Dark silicon and the end of multicore scaling. In ISCA, pages 365-376, 2011.
9. K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge. Drowsy caches: simple techniques for reducing leakage power. In ISCA, pages 148-157, 2002.
10. Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar. A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro, 27(5):51-61, 2007.
11. ITRS. Process Integration, Devices, and Structures (PIDS). http: //www.itrs.net/Links/2013ITRS/2013Tables/PIDS"-2013Tables.xlsx, 2013.
12. H. Jang et al. A hybrid buffer design with STT-MRAM for on-chIP interconnects. In NoCS, pages 193-200. IEEE, 2012.
13. A. Jog et al. Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. In DAC, pages 243-252. ACM, 2012.
14. J. P. Kim et al. A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance. In VLSIC, pages 296-297. IEEE, 2011.
15. E. Kitagawa et al. Impact of ultra low power and fast write operation of advanced perpendicular MTJ on power reduction for high-performance mobile CPU. In IEDM, pages 29-4. IEEE, 2012.
16. H. Matsutani, M. Koibuchi, D. Wang, and H. Amano. Run-time power gating of on-chIP routers using look-ahead routing. In ASPDAC, pages 55-60, 2008.
17. G. Michelogiannakis and W. J. Dally. Elastic buffer flow control for on-chIP networks. IEEE Transactions on Computers, 62(2):295-309, 2013.
18. T. Moscibroda and O. Mutlu. A case for bufferless routing in on-chIP networks. In ISCA, volume 37, pages 196-207, 2009.
19. U. Y. Ogras, R. Marculescu, P. Choudhary, and D. Marculescu. Voltage-frequency island partitioning for GALS-based networks-on-chIP. In DAC, pages 110-115, 2007.
20. T. Ohsawa et al. A 1.5 nsec/2.1 nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories. In VLSIT, pages C110-C111. IEEE, 2013.
21. H. Patil, R. Cohn, M. Charney, R. Kapoor, A. Sun, and A. Karunanidhi. Pinpointing representative portions of large IntelR ItaniumR programs with dynamic instrumentation. In MICRO, pages 81-92, 2004.
22. M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. Vijaykumar. Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories. In ISLPED, pages 90-95, 2000.
23. A. Samih et al. Energy-efficient interconnect via router parking. In HPCA, pages 508-519. IEEE, 2013.
24. C. Sun et al. DSENT-A tool connecting emerging photonics with electronics for opto-electronic networks-on-chIP modeling. In NOCS, pages 201-210, 2012.
25. M. B. Taylor et al. The Raw microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE Micro, 22(2):25-35, 2002.
26. S. K. Venkata, I. Ahn, D. Jeon, A. Gupta, C. Louie, S. Garcia, S. Belongie, and M. B. Taylor. SD-VBS: The San Diego vision benchmark suite. In IISWC, pages 55-64, 2009.
27. G. Venkatesh et al. Conservation cores: reducing the energy of mature computations. In ACM SIGARCH Computer Architecture News, volume 38, pages 205-218, 2010.
28. J. Zhan et al. Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems. TCAD, 33(11):1632-1643, 2014.
29. J. Zhan, Y. Xie, and G. Sun. NoC-Sprinting: Interconnect for fine-grained sprinting in the dark silicon era. In DAC, pages 1-6, 2014.