A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2013, Pages

  Ohsawa, T ^a   Miura, S ^b   Kinoshita, K ^a   Honjo, H ^b   Ikeda, S ^a   Hanyu, T ^a   Ohno, H ^a   Endoh, T ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

90-NM CMOS; DRIVE CURRENTS; EMBEDDED MEMORY; ERROR RATE; NON-VOLATILE; SHORT PERIODS; STT RAMS;

RANDOM ACCESS STORAGE;

EID: 84883439546     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. H. Ohno et al., IEDM, pp. 218-221, 2010.
2. S. Yamamoto et al., JJAP, p. 043001, 2009.
3. N. Sakimura et al., ISCAS, pp. 1971-1974, 2012.
4. J. Barth et al., IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 64-75, 2011.