A hybrid buffer design with STT-MRAM for on-chip interconnects

Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012

Volumn , Issue , 2012, Pages 193-200

  Jang, Hyunjun ^a   An, Baik Song ^a   Kulkarni, Nikhil ^a   Yum, Ki Hwan ^a   Kim, Eun Jung ^a  

^a Texas AandM University   (United States)

Author keywords

input buffer; Network on Chip; router; STT MRAM

Indexed keywords

BUFFER DESIGN; CHIP MULTIPROCESSORS; COMMUNICATION DELAYS; DATA MIGRATION; DESIGN ISSUES; DYNAMIC POWER; DYNAMIC POWER CONSUMPTION; HIGH DENSITY; HIGH DENSITY MEMORY; HIGH POWER CONSUMPTION; HYBRID DESIGN; INPUT BUFFERS; LATENCY REDUCTION; LEAKAGE POWER; MAGNETIC RAMS; MANY-CORE ARCHITECTURE; MIGRATION SCHEME; NETWORK ON CHIP; ON-CHIP INTERCONNECTS; RETENTION TIME; SPIN TORQUE; STT-MRAM; SUITABLE SOLUTIONS; WRITE OPERATIONS;

DESIGN; MICROPROCESSOR CHIPS; MRAM DEVICES; SERVERS; STATIC RANDOM ACCESS STORAGE; VLSI CIRCUITS;

ROUTERS;

EID: 84862736914     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2012.30     Document Type: Conference Paper

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