Variation-tolerant and disturbance-free sensing circuit for deep nanometer STT-MRAM

IEEE Transactions on Nanotechnology

Volumn 13, Issue 6, 2014, Pages 1088-1092

  Kang, Wang ^a,b   Li, Zheng ^a   Klein, Jacques Olivier ^b   Chen, Yuanqing ^a   Zhang, Youguang ^a   Ravelosona, Dafine ^b   Chappert, Claude ^b   Zhao, Weisheng ^a,b  

^a BEIHANG UNIVERSITY   (China)

^b UNIVERSITÉ PARIS SACLAY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); COMPUTER SIMULATION; INTELLIGENT SYSTEMS; MAGNETIC DEVICES; RANDOM ACCESS STORAGE;

MAGNETIC RANDOM ACCESS MEMORY; MONTE- CARLO SIMULATIONS; RELIABILITY PERFORMANCE; SENSING CIRCUITS; SOURCE FOLLOWERS; SPIN TRANSFER TORQUE; STMICROELECTRONICS; TEMPERATURE VARIATION;

MRAM DEVICES;

EID: 84910112229     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2014.2357054     Document Type: Article

References (22)

1. C. Chappert, A. Fert, and F. N. Dau, "The emergence of spin electronics in data storage," Nature Mater., vol. 6, no. 11, pp. 813-823, 2007.
2. Y. Huai, "Spin-transfer torque MRAM (STT-MRAM): Challenges and prospects," AAPPS Bull., vol. 18, no. 6, pp. 33-40, Dec. 2008.
3. S. A. Wolf, D. D. Awschalom, R. A. Buhrman, J. M. Daughton, S. Von Molnar, M. L. Roukes, A. Yu. Chtchelkanova, and D. M. Treger, "Spintronics: A spin-based electronics vision for the future," Science, vol. 294, no. 5546, pp. 1488-1495, 2001.
4. Y. Umeki, K. Yanagida, S. Yoshimoto, S. Izumi, M. Yoshimoto, H. Kawaguchi, K. Tsunoda, and T. Sugii, "A 0.38-V operating STT-MRAM with process variation tolerant sense amplifier," in Proc. IEEE Asian Solid-State Circuits Conf., 2013, pp. 249-252.
5. T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "A 1-Mb STTMRAM with zero-array standby power and 1.5-ns quick wake-up by 8-b fine-grained power gating," in Proc. IEEE Int. Memory Workshop, 2013, pp. 80-83.
6. W. S. Zhao, X. Wang, H. Lee, and Y. Chen, "STT-RAM cell optimization considering MTJ and CMOS variations," IEEE Trans. Magn., vol. 47, no. 10, pp. 2962-2965, Oct. 2011.
7. W. S. Zhao, Y. Zhang, T. Devolder, J. Klein, D. Ravelosona, C. Chappert, and P. Mazoyer, "Failure and reliability analysis of STT-MRAM," Microelectron. Reliab., vol. 52, no. 9, 10, pp. 1848-1852, Sep. 2012.
8. F. Sun and T. Zhang, "Defect and transient fault-tolerant system design for hybrid CMOS/Nanodevice digital memories," IEEE Trans. Nanotechnol., vol. 6, no. 3, pp. 341-351, May 2007.
9. J. C. Slonczewski, "Current-driven excitation of magnetic multilayers," J. Magn. Magn. Mater., vol. 159, pp. L1-L7, Jun. 1996.
10. W. Zhao, C. Chappert, V. Javerliac, and J. Noziere, "High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits," IEEE Trans. Magn., vol. 45, no. 10, pp. 3784-3787, Oct. 2009.
11. J. Kim, K. Ryu, S. H. Kang, and S.-O. Jung, "A novel sensing circuit for deep submicron spin transfer torqueMRAM(STT-MRAM)," IEEE Trans. Very Large Scale Integr. Syst., vol. 20, no. 1, pp. 181-186, Jan. 2012.
12. D. Goql, C. Arndt, J. C. Barwin, A. Bette, J. DeBrosse, E. Gow, H. Hoenigschmid, S. Lammers, M. Lamorey, and Y. Lu, "A 16-MbMRAM featuring bootstrapped write drivers," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 902-908, Apr. 2005.
13. W. Kang, W. Zhao, J. Klein, Y. Zhang, C. Chappert, and D. Ravelosona, "High reliability sensing circuit for deep submicron spin transfer torque magnetic random accessmemory," Electron. Lett., vol. 49, pp. 1283-1285, 2013.
14. F. Ren, H. Park, C. Yang, and D. Markovic, "Reference calibration of body-voltage sensing circuit for high-speed STT-RAMs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 11, pp. 2932-2939, Nov. 2013.
15. J. Kim, T. Na, J. P. Kim, S. H. Kang, and S. O. Jung, "A split-path sensing circuit for spin torque transfer MRAM," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 3, pp. 193-197, Mar. 2014.
16. T. Na, J. Kim, J. P. Kim, S. H. Kang, and S. O. Jung, "An offset-canceling triple-stage sensing circuit for deep submicrometer STT-RAM," IEEE Trans. Very Large Scale Integr. Syst., vol. 22, no. 7, pp. 1620-1624, Jul. 2014.
17. K. C. Smith and A. S. Sedra, "The current conveyor-A new circuit building block," Proc. IEEE, vol. 56, no. 8, pp. 1368-1369, Aug. 1968.
18. K. Kotani, T. Shibata, and T. Ohmi, "CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 762-769, May 1998.
19. Manual of design kit for CMOS 40 nm, ST Microelectronics, Geneva, Switzerland, 2012.
20. Y. Zhang, W. Zhao, Y. Lakys, J. Klein, J. Kim, D. Ravelosona, and C. Chappert, "Compact modeling of perpendicular anistropy CoFeB/MgO magnetic tunnel junctions," IEEE Trans. Electron. Devices, vol. 59, no. 3, pp. 819-826, Mar. 2011.
21. Y. Zhang,W. Zhao,G. Prenat, T. Devolder, J.Klein, C. Chappert, B.Dieny, and D. Ravelosona, "Electrical modeling of stochastic spin transfer torque writing in magnetic tunnel junctions for memory and logic applications," IEEE Trans. Magn., vol. 49, no. 7, pp. 4375-4378, Jul. 2013.
22. SINGULUS technology. (Nov. 2012). A Vacuum Deposition System ROTARIS for Semiconductor and other R&D Applications. [Online]. Available: http://www.singulus.de.