Reference calibration of body-voltage sensing circuit for high-speed STT-RAMs

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 60, Issue 11, 2013, Pages 2932-2939

  Ren, Fengbo ^a   Park, Henry ^a   Ken Yang, Chih Kong ^a   Markoviæ, Dejan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Body voltage sensing; CMOS; Magnetic tunnel junction (MTJ); Nonvolatile memory; Read margin; Reference calibration; Sensing margin; Spin transfer torque random access memory (STT RAM)

Indexed keywords

CALIBRATION; CMOS INTEGRATED CIRCUITS; MAGNETIC DEVICES; SPICE; TIMING CIRCUITS; TUNNEL JUNCTIONS;

BODY VOLTAGE; MAGNETIC TUNNEL JUNCTION; NON-VOLATILE MEMORY; READ MARGIN; SENSING MARGIN; SPIN-TRANSFER TORQUE RANDOM ACCESS MEMORY (STT-RAM);

RANDOM ACCESS STORAGE;

EID: 84887127551     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2013.2252653     Document Type: Article

References (23)

1. G. De Sandre et al., "A 4 Mb LV MOS-selected embedded phase change memory in 90 nm standard CMOS technology," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 52-63, Jan. 2011.
2. W. Otsuka et al., "A 4Mb conductive-bridge resistive memory with 2.3 GB/s read-throughput and 216 MB/s program-throughput," in Proc. Int. Solid-State Circuits Conf., San Francisco, CA, USA, 2011, pp. 210-211.
3. K. Tsuchida et al., "A 64MbMRAM with clamped-reference and adequate-reference schemes," in Proc. Int. Solid-State Circuits Conf., San Francisco, CA, USA, 2010, pp. 258-259.
4. Y. Pan et al., "Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications," in Proc. 18th Int. Symp. High Perform. Comput. Archit. (HPCL'12), New Orleans, LA, USA, 2012, pp. 1-10.
5. Y. Pan et al., "On the case of using quasi-EZ-NAND flash memory to build future solid-state drives," IEEE Trans. Comput., 2012, to be published.
6. G. Dong et al., "Estimating information-theoretical NAND flash memory storage capacity and its implication to memory system design space exploration," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 9, pp. 1705-1714, 2012.
7. D. Smith et al., "Latest advances and roadmap for in-plane and perpendicular STT-RAM," in Proc. 3rd Int. Memory Workshop (IMW), Dallas, TX, USA, 2011, pp. 1-3.
8. Y. Pan, "Exploring the use of emerging nonvolatile memory technologies in future FPGAs," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2012, to be published.
9. F. Ren and D. Markovi', "True energy-performance analysis of the MTJ-based logic-in-memory architecture (1-Bit full adder)," IEEE Trans. Electron Devices, vol. 57, no. 5, pp. 1023-1028, May 2010.
10. C. Zhang et al., "Mapping channel estimation and MIMO detection in LTE-advanced on a reconfigurable cell array," in Proc. Int. Symp. Circuits Syst. (ISCAS), Seoul, Korea, 2012, pp. 1799-1802.
11. H. Wu et al., "A 60 GHz on-chip RF-interconnect with coupler for 5 Gbps Bi-directional communication and multi-drop arbitration," in Proc. IEEE Custom Integr. Circuits Conf. (CICC), San Jose, CA, USA, 2012, pp. 9-12.
12. W. Xu et al., "In-place FPGA retiming for mitigation of variational single-event transient faults," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 6, pp. 1372-1381, Jun. 2011.
13. C. Zhang et al., "Energy efficient MIMO channel pre-processor using a low complexity on-line update scheme," in Proc. IEEE NORCHIP, Copenhagen, Denmark, 2012, pp. 1-4.
14. N. Amini et al., "Experimental analysis of IEEE 802.15.4 for on/off body communications," in Proc. 22nd IEEE Symp. Personal Indoor Mobile Radio Commun. (PIMRC), Toronto, ON, Canada, 2011, pp. 2138-2142.
15. W. Xu et al., "eCushion: An eTextile device for sitting posture monitoring," in IEEE Int. Conf. Body Sensor Networks (BSN), Dallas, TX, USA, 2011, pp. 194-199.
16. K. Ono et al., "A disturbance-free read scheme and a compact stochastic-spin-dynamics-based MTJ circuit model for Gb-scale SPRAM," in Proc. IEEE Int. Electron Devices Meet., Baltimore, MD, USA, 2009, pp. 1-4.
17. F. Ren et al., "A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs)," in Proc. 13th Int. Symp. Quality Electron. Design (ISQED'12), Santa Clara, CA, USA, pp. 275-282.
18. M. F. Chang et al., "A 0.5 V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65 nm CMOS using low-voltage currentmode sensing scheme with 45 ns random read time," inProc. Int. Solid-State Circuits Conf., San Francisco, CA, USA, 2012, pp. 434-435.
19. H. Zhao et al., "Spin-torque driven switching probability density function asymmetry," IEEE Tran. Magn., vol. 48, no. 11, pp. 3818-3820, Nov. 2012.
20. R. Dorrance et al., "Scalability and design-space analysis of a 1T-1 MTJmemory cell for STT-RAMs," IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 878-887, Apr. 2012.
21. R. Dorrance et al., "Scalability and design-space analysis of a 1T-1MTJ memory cell," in Proc. ACM/IEEE Int. Symp. Nanoscale Arch. (NANOARCH'll), San Diego, CA, USA, Jun. 2011, pp. 32-36.
22. R. Kanj et al., "Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events," in IEEE/ACM Proc. 43rd Design Autom. Conf., Anaheim, CA, USA, 2006, pp. 69-72.
23. Z. Sun et al., "Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement," in IEEE/ACM Int. Conf. Comput.-Aid-Design, Brooklyn, OH, USA, 2010, pp. 432-437.