A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 1, 2012, Pages 181-186

  Kim, Jisu ^a   Ryu, Kyungho ^a   Kang, Seung H ^b   Jung, Seong Ook ^a  

^a Yonsei University   (South Korea)

^b QUALCOMM INC   (United States)

Author keywords

Balancing; Read disturbance; Sensing circuit; Sensing margin; Source degeneration; STT MRAM

Indexed keywords

READ DISTURBANCE; SENSING CIRCUITS; SENSING MARGIN; SOURCE DEGENERATION; STT-MRAM;

BALANCING; COMPUTER SIMULATION; SPICE;

MRAM DEVICES;

EID: 83655192784     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2088143     Document Type: Article

References (11)

1. M. Hosomi et al. , "A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-ram, " in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2005, pp. 459-462. (Pubitemid 46370888)
2. T. Kawahara, R. Takemura, H. Takahashi, and H. Ohno, "SPRAM (SPin-transfer torque RAM) design and its impact on digital systems, " in Proc. IEEE Int. Conf. Electronics, Circuits, and Systems (ICECS), 2007, pp. 1011-1014.
3. K. Miura et al. , "A novel SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write-current dispersion, " in Proc. Symp. VLSI Technology, 2007, pp. 234-235.
4. T. Kawahara et al. , "2 Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read, " IEEE J. Solid State Circuits, vol. 43, no. 1, pp. 109-120, 2008.
5. N. Rizzo, "Toggle and spin torque: MRAM at everspin technologies, " in Proc. Non-Volatile Memories Workshop, 2010.
6. A. Bette et al. , "Ahigh-speed 128 KbitMRAMcore for future universal memory applications, " IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 678-683, 2004.
7. D. Goql et al. , "A 16-MbMRAMfeaturing bootstrapped write drivers, " IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 902-908, 2005.
8. H. Nho, S. Yoon, S. S. Wong, and S. Jung, "Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation, " IEEE Trans. Circuit Syst. II, vol. 55, no. 9, pp. 907-911, 2008.
9. G. Jeong et al. , "A 0. 24 um 2. 0 V 1T1MTJ 16 kb NV magnetoresistance RAM with self reference sensing, " in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2003, pp. 128-129.
10. B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, "Yield and speed optimization of latch-type voltage sense amplifier, " IEEE J. Solid State Circuits, vol. 39, no. 7, pp. 1148-1158, 2004.
11. U. K. Klostermann et al. , "A perpendicular spin torque switching based MRAM for the 28 nm technology node, " in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2007, pp. 187-190.