Defect and transient fault-tolerant system design for hybrid CMOS/nanodevice digital memories

IEEE Transactions on Nanotechnology

Volumn 6, Issue 3, 2007, Pages 341-350

  Fei, Sun ^a,b   Tong, Zhang ^a,b  

^a IEEE   (United States)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

Bose Chaudhuri Hocquenghem (BCH) codes; Complementary metal oxide semiconductor (CMOS); Defect fault tolerance; Error correcting code (ECC); Hybrid digital memory; Nanodevice; Very large scale integration (VLSI) implementation

Indexed keywords

BOSE-CHAUDHURI-HOCQUENGHEM (BCH) CODES; ERROR CORRECTING CODE (ECC); HYBRID DIGITAL MEMORY; VERY LARGE SCALE INTEGRATION (VLSI) IMPLEMENTATION;

CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); COMPUTATIONAL COMPLEXITY; DATA STORAGE EQUIPMENT; ERROR CORRECTION;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 34248632540     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2007.893572     Document Type: Article

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