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Volumn 61, Issue 3, 2014, Pages 193-197

A split-path sensing circuit for spin torque transfer MRAM

Author keywords

Sensing circuit; sensing margin; spin torque transfer magnetic random access memory (STT MRAM); split path; yield

Indexed keywords

MAGNETIC RECORDING; MAGNETIC STORAGE; MONTE CARLO METHODS; MRAM DEVICES; RANDOM ACCESS STORAGE; TIMING CIRCUITS;

EID: 84897109728     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2013.2296136     Document Type: Article
Times cited : (28)

References (9)
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    • J. Kim, K. Ryu, S. H. Kang, and S.-O. Jung, "A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM), " IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 1, pp. 181-186, Jan. 2012.
    • (2012) IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol.20 , Issue.1 , pp. 181-186
    • Kim, J.1    Ryu, K.2    Kang, S.H.3    Jung, S.-O.4
  • 5
    • 84887127551 scopus 로고    scopus 로고
    • Reference calibration of body-voltage sensing circuit for high-speed STT-RAMs
    • Nov.
    • F. Ren, H. Park, C.-K. K. Yang, and D. Markovi, "Reference calibration of body-voltage sensing circuit for high-speed STT-RAMs, " IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 11, pp. 2932-2939, Nov. 2013.
    • (2013) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.60 , Issue.11 , pp. 2932-2939
    • Ren, F.1    Park, H.2    Yang, C.-K.K.3    Markovi, D.4
  • 6
    • 0031212817 scopus 로고    scopus 로고
    • Supply and threshold voltage scaling for low power CMOS
    • PII S001892009705302X
    • R. Gonzalez, B. M. Gordon, and M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS, " IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216, Aug. 1997. (Pubitemid 127559667)
    • (1997) IEEE Journal of Solid-State Circuits , vol.32 , Issue.8 , pp. 1210-1216
    • Gonzalez, R.1    Gordon, B.M.2    Horowitz, M.A.3
  • 9
    • 84873322812 scopus 로고    scopus 로고
    • A scaling roadmap and performance evaluation of in-plain and perpendicular MTJ based STT-MRAMs for high-density cache memory
    • Feb.
    • K. C. Chun, H. Zhao, J. D. Harms, T.-H. Kim, J.-P. Wang, and C. H. Kim, "A scaling roadmap and performance evaluation of in-plain and perpendicular MTJ based STT-MRAMs for high-density cache memory, " IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 598-610, Feb. 2013.
    • (2013) IEEE J. Solid-State Circuits , vol.48 , Issue.2 , pp. 598-610
    • Chun, K.C.1    Zhao, H.2    Harms, J.D.3    Kim, T.-H.4    Wang, J.-P.5    Kim, C.H.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.