-
1
-
-
79960029622
-
Latest advances and roadmap for in-plane and perpendicular STT-RAM
-
A. Driskill-Smith, D. Apalkov, V. Nikitin, X. Tang, S. Watts, D. Lottis, K. Moon, A. Khvalkovshiy, R. Kawakami, X. Luo, A. Ong, E. Chen, and E. Chen, "Latest advances and roadmap for in-plane and perpendicular STT-RAM, " in Proc. IEEE IMW, Monterey, CA, USA, 2011, pp. 1-3.
-
(2011)
Proc. IEEE IMW, Monterey, CA, USA
, pp. 1-3
-
-
Driskill-Smith, A.1
Apalkov, D.2
Nikitin, V.3
Tang, X.4
Watts, S.5
Lottis, D.6
Moon, K.7
Khvalkovshiy, A.8
Kawakami, R.9
Luo, X.10
Ong, A.11
Chen, E.12
Chen, E.13
-
2
-
-
83655192784
-
A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM)
-
Jan.
-
J. Kim, K. Ryu, S. H. Kang, and S.-O. Jung, "A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM), " IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 1, pp. 181-186, Jan. 2012.
-
(2012)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.20
, Issue.1
, pp. 181-186
-
-
Kim, J.1
Ryu, K.2
Kang, S.H.3
Jung, S.-O.4
-
3
-
-
84863641270
-
A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs)
-
F. Ren, H. Park, R. Dorrance, Y. Toriyama, C.-K. K. Yang, and D. Markovi, "A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs), " in Proc. 13th ISQED, Santa Clara, CA, USA, 2012, pp. 275-282.
-
(2012)
Proc. 13th ISQED, Santa Clara, CA, USA
, pp. 275-282
-
-
Ren, F.1
Park, H.2
Dorrance, R.3
Toriyama, Y.4
Yang, C.-K.K.5
Markovi, D.6
-
4
-
-
32944468715
-
Design considerations for MRAM
-
Jan.
-
T. M. Maffitt, J. K. DeBrosse, J. A. Gabric, E. T. Gow, M. C. Lamorey, J. S. Parenteau, D. R. Willmott, M. A. Wood, and W. J. Gallagher, "Design considerations for MRAM, " IBM J. Res. Develop., vol. 50, no. 1, pp. 25-49, Jan. 2006.
-
(2006)
IBM J. Res. Develop.
, vol.50
, Issue.1
, pp. 25-49
-
-
Maffitt, T.M.1
Debrosse, J.K.2
Gabric, J.A.3
Gow, E.T.4
Lamorey, M.C.5
Parenteau, J.S.6
Willmott, D.R.7
Wood, M.A.8
Gallagher, W.J.9
-
5
-
-
84887127551
-
Reference calibration of body-voltage sensing circuit for high-speed STT-RAMs
-
Nov.
-
F. Ren, H. Park, C.-K. K. Yang, and D. Markovi, "Reference calibration of body-voltage sensing circuit for high-speed STT-RAMs, " IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 11, pp. 2932-2939, Nov. 2013.
-
(2013)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.60
, Issue.11
, pp. 2932-2939
-
-
Ren, F.1
Park, H.2
Yang, C.-K.K.3
Markovi, D.4
-
6
-
-
0031212817
-
Supply and threshold voltage scaling for low power CMOS
-
PII S001892009705302X
-
R. Gonzalez, B. M. Gordon, and M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS, " IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216, Aug. 1997. (Pubitemid 127559667)
-
(1997)
IEEE Journal of Solid-State Circuits
, vol.32
, Issue.8
, pp. 1210-1216
-
-
Gonzalez, R.1
Gordon, B.M.2
Horowitz, M.A.3
-
7
-
-
0038528647
-
A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects
-
May
-
M. Durlam, P. J. Naji, A. Omair, M. DeHerrera, J. Calder, J. M. Slaughter, B. N. Engel, N. D. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K. W. Kyler, J. J. Ren, J. A. Molla, W. A. Feil, R. G. Williams, and S. Tehrani, "A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects, " IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 769-773, May 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.5
, pp. 769-773
-
-
Durlam, M.1
Naji, P.J.2
Omair, A.3
Deherrera, M.4
Calder, J.5
Slaughter, J.M.6
Engel, B.N.7
Rizzo, N.D.8
Grynkewich, G.9
Butcher, B.10
Tracy, C.11
Smith, K.12
Kyler, K.W.13
Ren, J.J.14
Molla, J.A.15
Feil, W.A.16
Williams, R.G.17
Tehrani, S.18
-
8
-
-
33847743417
-
A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM
-
1609379, IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
-
M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachino, C. Fukumoto, H. Nagao, and H. Kano, "A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM, " in Proc. IEEE IEDM, Washington, DC, USA, 2005, pp. 459-462. (Pubitemid 46370888)
-
(2005)
Technical Digest - International Electron Devices Meeting, IEDM
, vol.2005
, pp. 459-462
-
-
Hosomi, M.1
Yamagishi, H.2
Yamamoto, T.3
Bessho, K.4
Higo, Y.5
Yamane, K.6
Yamada, H.7
Shoji, M.8
Hachino, H.9
Fukumoto, C.10
Nagao, H.11
Kano, H.12
-
9
-
-
84873322812
-
A scaling roadmap and performance evaluation of in-plain and perpendicular MTJ based STT-MRAMs for high-density cache memory
-
Feb.
-
K. C. Chun, H. Zhao, J. D. Harms, T.-H. Kim, J.-P. Wang, and C. H. Kim, "A scaling roadmap and performance evaluation of in-plain and perpendicular MTJ based STT-MRAMs for high-density cache memory, " IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 598-610, Feb. 2013.
-
(2013)
IEEE J. Solid-State Circuits
, vol.48
, Issue.2
, pp. 598-610
-
-
Chun, K.C.1
Zhao, H.2
Harms, J.D.3
Kim, T.-H.4
Wang, J.-P.5
Kim, C.H.6
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