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Volumn 33, Issue 5, 1998, Pages 762-768

CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters

Author keywords

A D converter; Charge transfer preamplifier; Comparator; Dynamic latch; Low power

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; ELECTRIC VARIABLES MEASUREMENT; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; NUMERICAL METHODS;

EID: 0032073841     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.668991     Document Type: Article
Times cited : (43)

References (7)
  • 1
    • 0022306670 scopus 로고
    • An 8-MHz CMOS subranging 8-bit A/D converter
    • Dec.
    • A. G. F. Dihgwall and V. Zazzu, "An 8-MHz CMOS subranging 8-bit A/D converter," IEEE J. Solid-State Circuits, vol. SC-20, pp. 1138-1143, Dec. 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , pp. 1138-1143
    • Dihgwall, A.G.F.1    Zazzu, V.2
  • 2
    • 0025382945 scopus 로고
    • An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption
    • Jan.
    • S. Hosotani, T. Miki, A. Maeda, and N. Yazawa, "An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption," IEEE J. Solid-State Circuits, vol. 25, pp. 167-172, Jan. 1990.
    • (1990) IEEE J. Solid-State Circuits , vol.25 , pp. 167-172
    • Hosotani, S.1    Miki, T.2    Maeda, A.3    Yazawa, N.4
  • 3
    • 0027553563 scopus 로고
    • A 10-b 50-MHz pipelined CMOS A/D converter with S/H
    • Mar.
    • M. Yotsuyanagi, T. Etoh, and K. Hirata, "A 10-b 50-MHz pipelined CMOS A/D converter with S/H," IEEE J. Solid-State Circuits, vol 28, pp. 292-300, Mar. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , pp. 292-300
    • Yotsuyanagi, M.1    Etoh, T.2    Hirata, K.3
  • 4
    • 0027887674 scopus 로고
    • A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC
    • Dec.
    • K. Kusumoto, A. Matsuzawa, and K. Murata, "A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC," IEEE J. Solid-State Circuits vol 28, pp. 1200-1206, Dec. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , pp. 1200-1206
    • Kusumoto, K.1    Matsuzawa, A.2    Murata, K.3
  • 5
    • 0029723894 scopus 로고    scopus 로고
    • DC-current-free low-power A/D converter circuitry using dynamic latch comparators with divided-capacitance voltage reference
    • May
    • K. Kotani, T. Shibata, and T. Ohmi, "DC-current-free low-power A/D converter circuitry using dynamic latch comparators with divided-capacitance voltage reference," in 1996 IEEE Int. Symp. Circuits Syst., May 1996, vol. 4, pp. 205-208.
    • (1996) 1996 IEEE Int. Symp. Circuits Syst. , vol.4 , pp. 205-208
    • Kotani, K.1    Shibata, T.2    Ohmi, T.3
  • 6
    • 0031382921 scopus 로고    scopus 로고
    • CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power, high-accuracy comparators
    • June
    • _, "CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power, high-accuracy comparators," in Dig. Tech. Papers Symp. VLSI Circuits, June 1997, pp. 21-22.
    • (1997) Dig. Tech. Papers Symp. VLSI Circuits , pp. 21-22
  • 7
    • 0017012361 scopus 로고
    • High sensitivity charge-transfer sense amplifier
    • Oct.
    • L. G. Heller, D. P. Spampinato, and Y. L. Yao, "High sensitivity charge-transfer sense amplifier," IEEE J. Solid-State Circuits, vol. SC-11, pp. 596-601, Oct. 1976.
    • (1976) IEEE J. Solid-State Circuits , vol.SC-11 , pp. 596-601
    • Heller, L.G.1    Spampinato, D.P.2    Yao, Y.L.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.