A 16-Mb MR AM featuring bootstrapped write drivers

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 4, 2005, Pages 902-906

  Gogl, Dietmar ^a   Arndt, Christian ^a,b   Barwin, John C ^a,c   Bette, Alexander ^a   DeBrosse, John ^a,c   Gow, Earl ^a,c   Hoenigschmid, Heinz ^a,b   Lammers, Stefan ^a,b   Lamorey, Mark ^a,c   Lu, Yu ^a,d   Maffitt, Tom ^a,c   Maloney, Kim ^a,c   Obermaier, Werner ^a,b   Sturm, Andre ^a   Viehmann, Hans ^a,b   Willmott, Dennis ^a,c   Wood, Mark ^a,c   Gallagher, William J ^a,d   Mueller, Gerhard ^a,b   Sitaram, Arkalgud R ^a,b  

^a INFINEON TECHNOLOGIES   (United States)

^b INFINEON TECHNOLOGIES AG   (Germany)

^c IBM MICROELECTRONICS   (United States)

^d IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

1T1MTJ; Architecture; Bootstrap; Cell; Driver; Mb; Memory; MRAM

Indexed keywords

ARCHITECTURE; CMOS INTEGRATED CIRCUITS; DIODES; ELECTRIC CURRENTS; MICROPROCESSOR CHIPS; OPTIMIZATION; SIGNAL PROCESSING; SUBSTRATES;

16 MB; BOOTSTRAP; CELL; DRIVERS; ITIMTJ; MEMORY; MRAM;

RANDOM ACCESS STORAGE;

EID: 20844436606     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.842856     Document Type: Conference Paper

References (5)

1. A. Bette et al., "A high-speed 128 Kbit MRAM core for future universal memory applications," in Symp. VLSI Circuits Dig. Tech. Papers, 2003, pp. 217-220.
2. M. Durlam et al., "A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects," in Symp. VLSI Circuits Dig. Tech. Papers, 2002, pp. 158-161.
3. A. Sitaram et al., "A 0.18 μm logic-based MRAM technology for high performance nonvolatile memory applications," in Symp. VLSI Technology Dig. Tech. Papers, 2003, pp. 15-16.
4. M. Durlam et al., "A 0.18 μm 4Mb toggling MRAM," in IEDM Tech. Dig., 2003, p. 995.
5. D. Worledge, "Magnetic phase diagram of two identical coupled nano-magnets," Appl. Phys. Lett., vol. 84, no. 15, p. 2847, Apr. 2004.