Software-hardware cooperative DRAM bank partitioning for chip multiprocessors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 6289 LNCS, Issue , 2010, Pages 329-343

  Mi, Wei ^b   Feng, Xiaobing ^a   Xue, Jingling ^c   Jia, Yaocang ^a,b  

^a Institute of Computing Technology   (China)

^b UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

^c UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

Address Mapping; Cache Locality; Row Buffer Locality

Indexed keywords

ADDRESS MAPPING; CACHE LOCALITY; CHIP MULTIPROCESSOR; FOUR-CORE; HARDWARE AND SOFTWARE; MEMORY ACCESS LATENCY; MULTIPLE APPLICATIONS; PARTITIONING METHODS; ROW BUFFER LOCALITY; SIMULATION RESULT; SINGLE-THREADED; ADDRESS MAPPINGS;

MAPPING; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PARALLEL ARCHITECTURES; SYSTEMS ANALYSIS; ADAPTIVE SYSTEMS; BENCHMARKING; HARDWARE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 78149271363     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-15672-4_28     Document Type: Conference Paper

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