Handling the problems and opportunities posed by multiple on-chip memory controllers

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2010, Pages 319-330

  Awasthi, Manu ^a   Nellans, David W ^a   Sudan, Kshitij ^a   Balasubramonian, Rajeev ^a   Davis, Al ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

data placement; DRAM management; memory controller design

Indexed keywords

CONTROLLERS; DYNAMIC RANDOM ACCESS STORAGE; DYNAMICS; INTEGRATED CIRCUIT INTERCONNECTS; PARALLEL ARCHITECTURES;

ALLOCATION STRATEGY; DATA PLACEMENT; DYNAMIC PAGE MIGRATION; INTERCONNECT FABRICS; MEMORY ACCESS LATENCY; MEMORY ADDRESS SPACE; MEMORY CONTROLLER; NON UNIFORM MEMORY ACCESS;

MEMORY ARCHITECTURE;

EID: 78149234452     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1854273.1854314     Document Type: Conference Paper

References (60)

1. Perfmon2 Project Homepage. http://perfmon2.sourceforge.net/.
2. Performance of the AMD Opteron LS21 for IBM BladeCenter. ftp://ftp.software.ibm.com/eserver/benchmarks/wp-ls21-081506.pdf.
3. Intel 845G/845GL/845GV Chipset Datasheet: Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH). http://download.intel.com/design/ chipsets/datashts/29074602.pdf, 2002.
4. Micron DDR3 SDRAM Part MT41J512M4. http://download.micron.com/pdf/ datasheets/dram/ddr3/2Gb-DDR3-SDRAM.pdf, 2006.
5. D. Abts, N. Jerger, J. Kim, D. Gibson, and M. Lipasti. Achieving Predictable Performance through Better Memory Controller in Many-Core CMPs. In Proceedings of ISCA, 2009.
6. M. Awasthi, K. Sudan, R. Balasubramonian, and J. Carter. Dynamic Hardware-Assisted Software-Controlled Page Placement to Manage Capacity Allocation and Sharing within Large Caches. In Proceedings of HPCA, 2009.
7. C. Benia et al. The PARSEC Benchmark Suite: Characterization and Architectural Implications. Technical report, Department of Computer Science, Princeton University, 2008.
8. B. Bershad, B. Chen, D. Lee, and T. Romer. Avoiding Conict Misses Dynamically in Large Direct-Mapped Caches. In Proceedings of ASPLOS, 1994.
9. R. Chandra, S. Devine, B. Verghese, A. Gupta, and M. Rosenblum. Scheduling and Page Migration for Multiprocessor Compute Servers. In Proceedings of ASPLOS, 1994.
10. J. Chang and G. Sohi. Co-Operative Caching for Chip Multiprocessors. In Proceedings of ISCA, 2006.
11. M. Chaudhuri. PageNUCA: Selected Policies For Page-Grain Locality Management In Large Shared Chip-Multiprocessor Caches. In Proceedings of HPCA, 2009.
12. Z. Chishti, M. Powell, and T. Vijaykumar. Optimizing Replication, Communication, and Capacity Allocation in CMPs. In Proceedings of ISCA-32, June 2005.
13. S. Cho and L. Jin. Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. In Proceedings of MICRO, 2006.
14. J. Corbalan, X. Martorell, and J. Labarta. Page Migration with Dynamic Space-Sharing Scheduling Policies: The case of SGI 02000. International Journal of Parallel Programming, 32(4), 2004.
15. V. Cuppu and B. Jacob. Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance. In Proceedings of ISCA, 2001.
16. V. Cuppu, B. Jacob, B. Davis, and T. Mudge. A Performance Comparison of Contemporary DRAM Architectures. In Proceedings of ISCA, 1999.
17. W. Dally. Report from Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN), 2006. http://www.ece.ucdavis.edu/~ocin06/ .
18. X. Ding, D. S. Nikopoulosi, S. Jiang, and X. Zhang. MESA: Reducing Cache Conicts by Integrating Static and Run-Time Methods. In Proceedings of ISPASS, 2006.
19. H. Dybdahl and P. Stenstrom. An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors. In Proceedings of HPCA, 2007.
20. X. Fan, H. Zeng, and C. Ellis. Memory Controller Policies for DRAM Power Management. In Proceedings of ISLPED, 2001.
21. N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki. Reactive NUCA: Near-Optimal Block Placement And Replication In Distributed Caches. In Proceedings of ISCA, 2009.
22. E. Ipek, O. Mutlu, J. Martinez, and R. Caruana. Self Optimizing Memory Controllers: A Reinforcement Learning Approach. In Proceedings of ISCA, 2008.
23. ITRS. International Technology Roadmap for Semiconductors, 2007 Edition.
24. R. E. Kessler and M. D. Hill. Page Placement Algorithms for Large Real-Indexed Caches. ACM Trans. Comput. Syst., 10(4), 1992.
25. C. Kim, D. Burger, and S. Keckler. An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches. In Proceedings of ASPLOS, 2002.
26. Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter. ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers. In Proceedings of HPCA, 2010.
27. R. LaRowe and C. Ellis. Experimental Comparison of Memory Management Policies for NUMA Multiprocessors. Technical report, 1990.
28. R. LaRowe and C. Ellis. Page Placement policies for NUMA multiprocessors. J. Parallel Distrib. Comput., 11(2), 1991.
29. R. LaRowe, J. Wilkes, and C. Ellis. Exploiting Operating System Support for Dynamic Page Placement on a NUMA Shared Memory Multiprocessor. In Proceedings of PPOPP, 1991.
30. A. Lebeck, X. Fan, H. Zeng, and C. Ellis. Power Aware Page Allocation. In Proceedings of ASPLOS, 2000.
31. C. Lee, O. Mutlu, V. Narasiman, and Y. Patt. Prefetch-Aware DRAM Controllers. In Proceedings of MICRO, 2008.
32. J. Lin, Q. Lu, X. Ding, Z. Zhang, X. Zhang, and P. Sadayappan. Gaining Insights into Multicore Cache Partitioning: Bridging the Gap between Simulation and Real Systems. In Proceedings of HPCA, 2008.
33. W. Lin, S. Reinhardt, and D. Burger. Designing a Modern Memory Hierarchy with Hardware Prefetching. In Proceedings of IEEE Transactions on Computers, 2001.
34. G. Loh. 3D-Stacked Memory Architectures for Multi-Core Processors. In Proceedings of ISCA, 2008.
35. P. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner. Simics: A Full System Simulation Platform. IEEE Computer, 35(2):50-58, February 2002.
36. C. McCurdy and J. Vetter. Memphis: Finding and fixing numa-related performance problems on multi-core platforms. In Proceedings of ISPASS, 2010.
37. Micron Technology Inc. Micron DDR2 SDRAM Part MT47H128M8HQ-25, 2007.
38. R. Min and Y. Hu. Improving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addresses. IEEE Trans. Comput., 50(11), 2001.
39. N. Muralimanohar, R. Balasubramonian, and N. Jouppi. Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. In Proceedings of MICRO, 2007.
40. O. Mutlu and T. Moscibroda. Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. In Proceedings of MICRO, 2007.
41. O. Mutlu and T. Moscibroda. Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems. In Proceedings of ISCA, 2008.
42. M. Powell, M. Gomaa, and T. Vijaykumar. Heat-and-Run: Leveraging SMT and CMP to Manage Power Density Through the Operating System. In Proceedings of ASPLOS, 2004.
43. M. K. Qureshi. Adaptive Spill-Receive for Robust High-Performance Caching in CMPs. In Proceedings of HPCA, 2009.
44. N. Rafique, W. Lim, and M. Thottethodi. Architectural Support for Operating System Driven CMP Cache Management. In Proceedings of PACT, 2006.
45. S. Rixner, W. Dally, U. Kapasi, P. Mattson, and J. Owens. Memory Access Scheduling. In Proceedings of ISCA, 2000.
46. V. Romanchenko. Quad-Core Opteron: Architecture and Roadmaps. http://www.digital-daily.com/cpu/quad core opteron.
47. T. Sherwood, B. Calder, and J. Emer. Reducing Cache Misses Using Hardware and Software Page Placement. In Proceedings of SC, 1999.
48. A. Snavely, D. Tullsen, and G. Voelker. Symbiotic Jobscheduling with Priorities for a Simultaneous Multithreading Processor. In Proceedings of SIGMETRICS, 2002.
49. E. Speight, H. Shafi, L. Zhang, and R. Rajamony. Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors. In Proceedings of ISCA, 2005.
50. R. Swinburne. Intel Core i7 - Nehalem Architecture Dive. http://www.bit-tech.net/hardware/2008/11/03/intel-core-i7-nehalem-architecture- dive/.
51. D. Vantrease et al. Corona: System Implications of Emerging Nanophotonic Technology. In Proceedings of ISCA, 2008.
52. B. Verghese, S. Devine, A. Gupta, and M. Rosenblum. Operating system support for improving data locality on CC-NUMA compute servers. SIGPLAN Not., 31(9), 1996.
53. D. Wallin, H. Zeffer, M. Karlsson, and E. Hagersten. VASA: A Simulator Infrastructure with Adjustable Fidelity. In Proceedings of IASTED International Conference on Parallel and Distributed Computing and Systems, 2005.
54. D. Wang et al. DRAMsim: A Memory-System Simulator. In SIGARCH Computer Architecture News, September 2005.
55. D. Wentzlaff et al. On-Chip Interconnection Architecture of the Tile Processor. In IEEE Micro, volume 22, 2007.
56. M. Zhang and K. Asanovic. Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. In Proceedings of ISCA, 2005.
57. Z. Zhang, Z. Zhu, and X. Zhand. A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conicts and Exploit Data Locality. In Proceedings of MICRO, 2000.
58. H. Zheng et al. Mini-Rank: Adaptive DRAM Architecture For Improving Memory Power E ciency. In Proceedings of MICRO, 2008.
59. X. Zhou, Y. Xu, Y. Du, Y. Zhang, and J. Yang. Thermal Management for 3D Processor via Task Scheduling. In Proceedings of ICPP, 2008.
60. Z. Zhu and Z. Zhang. A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. In Proceedings of HPCA, 2005